PDSP16488AC datasheet(13/33 Pages) MITEL

13 / 33 page

Loading Registers from a Host CPU

The X14:0 expansion data inputs on a single or master device

are connected to the host bus to provide address and data for the

internal registers. In a multiple device system the remaining

devices receive addresses and data which have been passed

through the expansion connection between earlier devices in the

cascade chain. Each device needs an individual chip enable

( CE ) plus a global data strobe (DS), a read/ not write (R/W) line,

and PROG signal from the host.

Registers are individually addressed and can be loaded in any

sequence once the global PROG signal has been produced by the

host. The latter would normally be produced from an address decoder

encompassing all the necessary device addresses.

If a self-timed system is to be implemented, a timing strobe

must be passed down the expansion chain through

the PC0/PC1 connections. The PC0 output from the final device

is used as a host REPLY signal, and indicates that the last

device has received data after the propagation delay of previous

devices. The timing strobe is produced in the Master device from

the host data strobe, and will appear on the PC0 output. This

feature allows the user to cascade any number of devices without

having to know the propagation delay through each device. The

timing information for this mode of operation is given in Fig. 10.

The host can also read the data contained in the internal registers.

The required device is selected using chip enable with the R/W line

high, indicating a read operation. Single device systems output the

data read on X7:0, but in multiple device systems data is read from

the D7:0 outputs on the final device in the chain. These must be

connected back to the host data bus through tristate drivers, whose

tristate control must be generated externally (see Figs. 14 and 15).

When earlier devices in the chain are addressed, the register

contents are transferred through the expansion connections down to

the final device. In the self timed configuration the data will be valid

when REPLY is taken low by PC1 , as shown in Fig. 10.

If REPLY is not to be used, the PC0/PC1 connections are

not necessary, and the host data strobe for a write operation must

be wide enough to allow for the worst case propagation delay

through all the devices (tDEL). If the data or address from the host

does not meet the set up time given in Fig. 8, the width of the data

strobe can be simply extended to compensate for the additional

delay. When reading data the access time required is

tACC tDEL(N 1), using the maximum times given in the Host

Mode Switching Characteristics.

Host control lines

X7:0

8-bit data bus. In a Single device system this bus is

bidirectional; in other configurations it is an input.

Only a Single or Master device is connected directly

to the host. Other devices receive data from the

output of the previous device in the chain.

X14:8

7-bit address bus which is used to identify one of the

73 internal registers. Connected in the same man-

ner as X7:0.

X15

X15 must be open circuit on the Master device

An input from the previous PC1 output in a multiple

device chain. Not needed on a Single device or if the

self timed feature is not used.

Reply to the host from a Single device or from the

last device in a cascade chain. It indicates that the

write strobe can be terminated. Connected to PC0

input of the next device at intermediate points in the

chain if the self timed feature is used.

PROG

R/W

Read/Not Write line from the host CPU which is

connected to all devices in the system.

An active low enable which is normally produced

from a global address decode for the particular

device. This must encompass all internal register

addresses.

An active low host data strobe which is connected to

all devices in the system.

An active low global signal, produced by the host,

which is connected to all devices in the system.

Together with a unique chip enable for every device,

it allows the internal registers to be updated or

examined by the host PROG and CE should be tied

together in a Single device system.

Loading Registers from an EPROM

In the EPROM mode, one device has to assume the role of

a host computer. If more than one device is present, this must be

the first component in the chain, which must have its MASTER

pin tied low.

The Master device contains internal address counters which

allow the registers in up to 16 cascaded PDSP16488As to be

specified. It also generates the PROG signal and a data strobe

on the pins which were previously inputs. These outputs must be

connected to the other devices in the system, which still use them

as inputs. The R/W input should be tied low on all devices.

The width of the data strobe is determined by the feedback

connection from the PC1 output on the last device to the PC0 input

on the Master. The PC0/PC1 connections must be made be-

tween devices in a multiple device system; in a single device

system the connection is made internally.

The available EPROM access time is determined by an

internal oscillator and does not require the pixel clock to be

present during the programming sequence. Any pixel clock re-

synchronization in a real time system will thus not affect the

coefficient load operation. The relevant EPROM timing informa-

tion is shown in Fig. 11.

The load procedure will commence after RES has gone from

low to high, and will be indicated by the PROG output going

low. The data from 73 EPROM locations will be loaded into the

internal registers using addresses corresponding to those in

Table 5. Within a particular page of 128 EPROM locations, the

first nine locations supply control register information, and the

top 64 supply coefficients. The middle 55 locations are not

used. If the window size is 8 4, the top 32 locations will also

contain redundant data, and if the size is 4

4 the top 48 will

be redundant.

In a multiple device system the load sequence will be re-

peated for every device, and four additional address bits will be

generated on the CS3:0 pins. These address bits provide the

EPROM with a page address, with one page allocated to each

device in the system. Within each page only 73 locations provide

data for a convolver, the remainder are redundant as in the single

device system. The CS3:0 outputs must also be decoded in order

to provide individual chip enables for each device. These can

readily be derived by using an AS138 TTL decoder. Bits in an

internal control register determine the number of times that the

sequence is repeated.

If changes to the convolver operation are to be made after

power-on, activating the CE input on the Master or Single

device will instigate the load procedure. Additional EPROM

address bits supplied from the system will allow different filter

coefficients to be used.

PC0

PC1

PDSP16488AC Datasheet(PDF) 13 Page - Mitel Networks Corporation

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