PDSP16488GC datasheet(22/33 Pages) MITEL

22 / 33 page

The least significant 8 bits of the pixel are connected to the

Master device and the most significant 8 bits are connected to the

device producing the final result.. The internal sum in this device

must be delayed by four pixels to match the delay in the

expansion output from the first device. This is actually achieved

by delaying the pixel inputs to the line stores (register D, bits 4:2,

= 001). The expansion input needs no additional delay (register

D, bits 1:0, = 10).

The actual pixel precision can be any number of pixels

between 8 and 16, and may be a signed or unsigned number. Any

unused, more significant bits, must respectively be either sign

extended or be tied low.

DELOP must have four additional pipeline delays in order to

match the total processing delay. This output can be obtained

from either device.

Four device systems

Four devices, each in the 8 8 mode, can be used to provide

a 16 16 window, with 8-bit pixel resolution and 10MHz clock

rates. The partial sum from the first device in each row must be

delayed by eight pixel clocks before it is added to the result from

the next device. This provides the eight pixel displacement to

match the width of the window. The delay is actually provided by

four additional delays in the expansion input to the next device,

plus the inherent four clock delays in outputting results from the

first device. Register D, bit 0 controls the additional delay.

The internal convolver sums, in the two devices in the second

row, must be delayed by 12 clocks before they are added to the

result from the first row. This twelve clock delay is necessary

because of the combination of the eight pixel horizontal displace-

ment delay, and the four clock delay in outputting the result from

the last device in the top row. It is actually achieved by delaying

the pixel inputs to the line stores (register D, bits 3:2, = 11).

The DELOP output must have 20 delays additional to those

in a single device. This compensates for the twelve delays added

to the convolver sums in the second row, plus an additional eight

delays to compensate for the partial width of the first device in the

second row.

Four devices can also be used to give an 8 8 window, but

with a 30MHz pixel clock. Each device is configured to provide

a 4 4 partial window, but the maximum pixel rate is reduced from

40 to 30MHz because of the response of the line delay expansion

circuitry. Intermediate precision is restricted to 16 bits, since time

multiplexed data outputs cannot be used above 20MHz.

This configuration requires no additional delay in the expan-

sion inputs, and the inputs to the line stores both devices in the

second row must be delayed by 8 clock cycles (register D, bits

3:2, = 10). The DELOP output needs twelve additional clock

delays to match the processing delay.

Figs. 16 and 17 show non-interlaced and interlaced versions

of the above 8 8 and 4 4 arrangements

Fig. 18 shows how four devices can also be used to provide

an 8 8 window, with 16-bit pixels and 20MHz clock rates. The

expansion data from a previous device needs no additional delay

since the partial window size in each device is only 4 4. The

internal convolver sums from third and fourth devices must be

delayed by 8 clocks and the DELOP output must have 12

additional delays. If this arrangement is to be used in a non-

interlaced application, the field store must be replaced by four line

delays.

Six device systems

As shown in Fig. 19, six devices, each in an 8W 4D mode

using 8-bit pixels, can provide a 16W 12D window at 20MHz

clock rates. Expansion inputs from previous devices in a row (but

not the first device in each row) need an extra 4 clocks of delay

since the partial window is eight pixels wide. Internal convolver

sums need a differential delay of 12 clock cycles from row to row

(register D, bits 3:2, = 11).

The DELOP output must have 32 additional delays to match

the total processing delay.

Eight device systems

Two additional chips will extend the above six device configu-

ration to a 16 16 window. Internal convolver sums must have

differential delays of 12 clock cycles between rows, as in the six

device system. The DELOP output needs 44 additional clock

delays.

Nine device systems

Nine devices each in the 8 8 mode will provide a 24 24

window with 8- bit data and 10MHz pixel clocks. This is

shown in Fig. 20. Expansion data inputs from previous

devices in a row (but not the first device in each row) need

an extra 4 clocks of delay, controlled by register D, bit 0 The

internal convolver sums need differential delays of 20 clock

cycles between rows. Sixteen of the latter delays can be

provided internally by setting register B, bit 3 and also

externally.

The DELOP output needs 56 clock delays in addition to

the 29 required for the 8 8 single device configuration.

PDSP16488GC Datasheet(PDF) 22 Page - Mitel Networks Corporation

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