PDSP16510GCPR datasheet(19/25 Pages) MITEL

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PDSP16510

USER NOTES - STOPPING DOS

(1) GENERAL DESCRIPTION

The transform is calculated internally fully synchronous to

SCLK. However, as all outputs are referenced to DOS, a

transfer has to be made between the two clocks. In addition,

some dummy DOS strobes are needed to operate the internal

control logic, and to advance data from the internal RAMs to

the output pins.

The most simple configuration for the device is to have

DOS running continuously and for DEN to be permanently

active. When this happens the user will just be aware of data

appearing on the output pins on the same DOS cycle when

DAV goes active. However, there are many situations where

either DOS is not continuously running, or DEN is not

permanently active. To help explain how to operate the device

in these situations, the internal operation of the output circuits

must be described. For those who are not going to be

interrupting DOS, the remainder of this section can be

ignored.

(2) INTERNAL RAM - GENERAL DESCRIPTION.

For single device operation of transforms less than 1024

points, the internal RAM is shared between three separate

operations which enable the device to output old transformed

results, calculate the current transform, and input new data

ready for the next transform. All these operations, along with

the internal control logic, are controlled by a 12-cycle state

machine. The RAM operations are:

(a) 2 cycles in every 12 are dedicated to reading new

information in the input buffer and writing it to the RAM.

(b) 2 cycles in every 12 are dedicated to reading the

contents of the RAM and advancing that data to the

output buffer.

operations of the transform currently being calculated.

(3) SEQUENCE OF EVENTS

The sequence of events relating to the output control and

data flow is as follows :

(3.1)

An SCLK rising edge :

(a) An internal flag is raised to indicate that the

transform has finished and data is available to be

dumped. Data will be present in the internal RAM,

and the output address generator will be at the

correct address. Access to the RAM at this

moment, however, has not been made.

(b) If at this moment the device is programmed to be a

single device, and DEN is inactive, then DAV will be

made active - ie without the presence of DOS. If

DEN is active at this point, or the device is

programmed in any multiple device mode, then

DAV will remain inactive.

(3.2)

Accessing the RAM at this point

At this moment, when DAV has been made active

before data appears on the output pins, data is not yet

in the output buffer. Internally the precise SCLK cycle

at which the RAMs are read and written to the output

buffers now has to be waited for. This cycle, as

described above occurrs 2 in every 12 SCLK cycles, so

at worst case 6 SCLK cycles have to elapse until data

is guaranteed to be in the output buffer.

If the DOS rate is similar to the SCLK rate, and the user

has been immediately applying DOS pulses (on

seeing DAV go active) hoping to get data off the chip,

then this will not actually happen.

The next internal flag raised is the one which indicates

that the output data has been successfully read from

the RAMs and is now in the output buffer.

(3.3)

The next DOS rising edge (regardless of DEN status)

The flag indicating that the RAMs have been read is

transferred to circuitry operating on DOS. The output

enable signal, DEN, does not have to be present at this

point.

(3.4)

The next DEN-Enabled DOS rising edge (ie the 1st one

of this sequence)

The output state machine receives it's first edge.

(3.5)

The next DEN-Enabled DSO rising edge (ie the 2nd)

Internal output address generators start to count

(ready for fetching the next set of output data).

(3.6)

The next DEN-Enabled DOS rising edge (ie the 3rd)

An enable signal is raised for the final data latch in the

output buffer.

(3.7)

The next DEN-Enabled DOS rising edge (ie the 4th)

(a) The final data in the output buffer latch clocks-

through new data and presents it to the output

pads.

(b) The output pads come output of high impedance

active.

PDSP16510GCPR Datasheet(PDF) 19 Page - Mitel Networks Corporation

PDSP16510GCPR Datasheet(HTML) 19 Page - Mitel Networks Corporation

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