PDSP16515A

13

The output of the FIFO must provide data for the real inputs.

Continuous inputs can still be accepted, and each block will

initially occur on the imaginary inputs, and then occur again on

the real inputs as an output from the FIFO. The data output

sequence will consist of the results from a pair of inputs,

followed by the results obtained after the required overlap.

Thus with 50% overlapping the sequence is 1 & 2 followed by

1.5 & 2.5 followed by 3 & 4 followed by 3.5 & 4.5 etc., where

1 2 3 4 are the sequential inputs to the external FIFO, 1.5 is the

overlap between 1 & 2, and 2.5 is the overlap between 2 & 3.

When eight simultaneous 64 point transforms are performed,

the sampling rates given in Table 5 assume that data is from

a common source. The data outputs will be in the correct

sequence from 1 to 8, corresponding to inputs 1 through 8 in

normal order from a single source. When data is from two

sources the sampling rates will be halved, and the output

sequence will be 1A 1B 2A 2B 3A 3B 4A 4B, where A and B

are the dual simultaneous sources on the real and imaginary

inputs respectively. If data block overlapping is used in either

of the above cases, the eight outputs will be followed by results

from the same basic eight blocks but time displaced to give the

required overlap. If more than two sources are to be handled

the user must provide appropriate buffering and multiplexing,

and the sampling rates must be proportionally reduced.

When two 1024 point transforms are performed with a single

device, on data from a single source, the input buffer must be

arranged to acquire two blocks before initialising a transfer to

the device. In order to improve the maximum sampling rates

possible, data should be read simultaneously from each half

of the buffer, and loaded into the real and imaginary inputs.

This halves the transfer time from the buffer to the device, but

requires the device to expect dual inputs. Thus if block

overlapping is not needed Control Register Bits 8:6 should be

set to 101.

With 1024 point transforms all block overlaps are handled by

the buffer logic, and not by the internal RAM, but the device

must still be programmed to expect the required overlap if the

external buffer makes use of the in-active LFLG edge to mark

the overlap point. To achieve the performance given in Table

5 with 50% overlaps, the buffer must provide sufficient storage

for at least 2.5 data blocks. With 75% overlaps it must provide

storage for 2.75 blocks. This extra storage allows transfers

between devices to be only needed when a complete new

block has been acquired for 50% overlaps, and when half a

new block has been acquired for 75% overlaps.If storage is

restricted to two data blocks, only half the sampling rates given

will be possible. Transfers between devices must then occur

when a half or a quarter of a new block has been acquired.

Since the minimum time between transfers must be no less

than the transform time itself, the sampling rates must be

proportionally reduced to prevent loss of data.

Configuration

Clock Periods

16 X 16PT

COMP

456

4 X 64PT

COMP

660

256PT

COMP

852

1024PT

COMP

3943

8 X 64PT

REAL

852

2 X 256PT

REAL

1068

2 X 1024PT

REAL

4735

Table 5 : Guide to MAX Sampling rates (in MHz) possible from a single device system, ASSUMMING

SCLK is 40 MHz.

SIingle Device Sampling Rates

In a single device system the maximum sampling rate is

dependent on the transform size, the data overlap, and

whether real or complex data is applied. Table 4 gives the

times taken to complete the transforms for the various block

sizes, which include an allowance for synchronisation

between the DIS strobe and the system clock. If continuous

data is to be transformed, the time to acquire a new block of

data (or partial block with overlapping) must be at least equal

to these transform times. Load and dump times must also be

added in the 1024 modes. For non continuous transforms the

peak rate is limited by the system clock rate and the factor , F,

given previously.

The time taken to dump the transformed data must be no more

than the load time, if continuous inputs are to be supported and

I/O operations are concurrent with transforms. With block

overlapping the dump time must be reduced to the time taken

to load the partial block. This dump time must include four

extra DOS strobes needed to prime the output circuitry when

a transform is complete. These, in effect, can be added to the

transform time such that with concurrent I/O and 0%, 50%, or

75% overlapping;

nS or (nS)/2 or (nS)/4 must be gtr than or equal to PK + 4W

where n is the transform size, S is the input DIS period, P is

the number of clock periods given in Table 4, K is the system

clock period, and W is the DOS period which can be less than

S if necessary. Note also that S must be synchronous to

SCLK,

When DIS and DOS are produced from a common source the

minimum allowable sampling period must be increased to

allow for the extra dumping time. Thus when DIS and DOS

have equal periods and, for example, there is no overlapping;

(n - 4)S must be greater than or equal to PK

Table 4. Computation Times in Clock Periods

23.9

-

-

16.1 8.0

4.0

12.3

6.1

3.0

6.8

3.4

1.7

24.6

12.3

6.1

19.5

9.7

4.3

12.1

6.0

3.0

0%

50%

75%

16 X 16 COMPLEX

4 X 64 COMPLEX

1024 COMPLEX

256 COMPLEX

0%

50%

75%

0%

50%

75%

0%

50%

75%

0%

50%

75%

8 X 64 REAL

2 X 256 REAL

2 X 1024 REAL

0%

50%

75%

0%

50%

75%