VP520S

2

VIDEO COMPRESS MODE ( DECIMATE )

This mode is used when CCIR601 video is to be converted

to CIF or QCIF spatial resolution prior to compression. Incom-

ing luminance and chrominance data does not need any prior

buffering, but must meet the timing requirements given in

Figure 2. A bit in Control register 1 allows the Cb component

to precede the Cr component if necessary. This data is passed

through vertical and horizontal decimating filters before it is

stored in an external frame store. When a complete field has

been decimated it is read out in macroblock format and

transferred to the next system component.

In this mode HREF, VREF, and FREF are normally inputs

which are used to reference active video with respect to video

synchronization pulses. The active going edges are used

internally, and these must meet the set up time with respect to

the system clock as given in Figure 2. Stable inputs are

needed with no jitter due to asynchronous pixel clocks, but

when this is not possible an external FIFO can be used plus

two extra signals as described later. The reference inputs

need only stay active for one system clock period. Note that

the active going edges for HREF and VREF can individually

be defined to be high going or low going, through two bits in

Control Register 0. Also note that CREF is always an input and

is used as a qualifier for SCLK. The actual edges of CREF are

not used.

The internal sync generator can still be used in this mode,

if there is a need to supply sync to the video source. The HREF

and VREF pins are then used to output HSYNC and VSYNC.

Composite sync is supplied on the CSYNC pin.

In addition the CLMP pin provides a pulse [13 SCLK's

wide] which can be used to DC restore the black level in an A/

D converter. It is active high during the back porch.

The horizontal blanking output (HBLANK) defines when

the device expects the first pixel in a line to be supplied, and

is derived from the user supplied HREF input. The delay

between HREF and HBLANK is user definable in multiples of

CREF periods. If the defined value is zero then the HREF input

must be horizontal blanking with the minimum set time speci-

fied. The HBLANK output is then not defined.

All data changes are referenced to the system clock. The

edge actually used is indicated by the CREF input signal,

which has a period of double the clock period. The VP520S will

strobe in data on the rising edge of the system clock which

occurs whilst CREF is high.

PIN DESCRIPTION

NAME

TYPE

FUNCTION

Y7:0

I/O

Luminance input or output bus

C7:0

I/O

Chrominance input or output bus

M7:0

I/O

Macroblock input or output bus

D15:0

I/O

16 bit data bus for DRAM frame store

A7:0

O

Multiplexed address bus to the DRAM

A8

O

Most sig address bit or second CAS

RAS

O

Row strobe for the DRAM's

CAS

O

Column strobe for the DRAM's

R/

W

O

Read/ write signal to the DRAM's

HREF

I/O

Horiz. reference in or horiz. sync out

VREF

I/O

Vertical reference in or vertical sync out

CREF

I/O

CREF in or CREF out

FREF

I/O

Field Indicator in or out

HBLNK

O

Horizontal Blanking output

CSYNC

O

Composite sync output in free run mode

CLMP

O

Defines a black level clamping period

for A/D converters

VRST

Frame start identifier. If FRST is low

then a low going edge will reset the

internal sync generator.

FRST

Field identifier

REQYUV

I

Request macroblocks from encoder

MCLK

I/O

Macroblock I/O strobe

FSIG

I/O

Frame start/ ready signal

SCLK

I

System Clock. 27MHz in PAL/NTSC

systems

HD7:0

I/O

Host data bus

HA3:0

I

Host controller address bits

RD

I

An active low host read strobe

WR

I

An active low host write strobe

CEN

I

An active low enable for the strobes

RST

I

Power on reset

TDI

I

JTAG I/P data

TDO

O

JTAG O/P data

TMS

I

Test mode select

TCK

I

JTAG clock

TRST

I

JTAG reset

TOE

I

When high all O/P's are high

impedance

NOTE:

"Barred" active low signals do not appear with a bar in the main

body of the text.

Fig 2 : Luminance and chrominance inputs in the decimate mode.

10ns

min

10ns min

HBLNK

O/P

2ns

min

10ns

min

HREF

INPUT

PROGRAMMED DELAY

INPUT

CLOCK

First Cb Comp.

2ns

min

First Cr Comp.

CHROM

INPUT

Second I/P

First I/P

LUM

INPUT

10ns

min

2ns

min

CREF

INPUT