GD25Q80 datasheet(21/49 Pages) ELM

21 / 49 page

Rev.1.0

49 -

http://www.elm-tech.com

GD25Q80CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash

7.11. Quad I/O Fast Read (EBH)

The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to

input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock

by IO0, IO1, IO2, IO3, each bit being latched in during the rising edge of SCLK, then the memory contents

are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed

Figure13. The first byte addressed can be at any location. The address is automatically incremented to the next

higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must

be set to enable for the Quad I/O Fast read command.

Quad I/O Fast Read with “Continuous Read Mode”

The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous

Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0)

=AXH, then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the

EBH command code. The command sequence is shown in followed Figure14. If the “Continuous Read Mode”

bits (M7-0) are any value other than AXH, the next command requires the first EBH command code, thus

returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before

issuing normal command.

Figure 13. Quad I/O Fast Read Sequence Diagram (M7-0 = 0XH or not AXH)

Command

0 1 2 3 4 5 6 7

EBH

CS#

SCLK

SI(IO0)

SO(IO1)

8 9 10 11 12 13 14 15

4 0 4 0 4 0 4 0

16 17 18 19 20 21 22 23

4 0 4 0

5 1 5 1 5 1 5 1

5 1 5 1

A23-16 A15-8 A7-0 M7-0

6 2 6 2 6 2 6 2

6 2 6 2

7 3 7 3 7 3 7 3

7 3 7 3

WP#(IO2)

HOLD#(IO3)

Dummy

Byte1 Byte2

Figure 14. Quad I/O Fast Read Sequence Diagram (M7-0 = AXH)

0 1 2 3 4 5 6 7

CS#

SCLK

8 9 10 11 12 13 14 15

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

4 0 4 0

5 1 5 1

6 2 6 2

7 3 7 3

4 0 4 0

5 1 5 1

6 2 6 2

7 3 7 3

4 0 4 0

5 1 5 1

6 2 6 2

7 3 7 3

A23-16 A15-8 A7-0 M7-0

Dummy

Byte1 Byte2

GD25Q80 Datasheet(PDF) 21 Page - ELM Electronics

GD25Q80 Datasheet(HTML) 21 Page - ELM Electronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL