PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B

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4

Pin Configuration for PCS3P623Z09A/B

16

15

14

13

12

11

10

9

DLY_CTRL

CLKOUTA4

CLKOUTA3

VDD

GND

CLKOUTB4

CLKOUTB3

S1

PCS3P623Z09A/B

1

2

3

4

5

6

7

8

CLKIN

CLKOUTA1

CLKOUTA2

VDD

GND

CLKOUTB1

CLKOUTB2

S2

Table 2. PIN DESCRIPTION FOR PCS3P623Z09A/B

Pin #

Pin Name

Pin Type

Description

1

CLKIN (Note 5)

I

External reference Clock input, 5 V tolerant input

2

CLKOUTA1 (Note 6)

O

Buffered clock Bank A output (Note 8)

3

CLKOUTA2 (Note 6)

O

Buffered clock Bank A output (Note 8)

4

VDD

P

3.3 V supply

5

GND

P

Ground

6

CLKOUTB1 (Note 6)

O

Buffered clock Bank B output (Note 8)

7

CLKOUTB2 (Note 6)

O

Buffered clock Bank B output (Note 8)

8

S2 (Note 7)

I

Select input, bit 2. See Select Input Decoding table for PCS3P623Z09 for more details

9

S1 (Note 7)

I

Select input, bit 1. See Select Input Decoding table for PCS3P623Z09 for more details

10

CLKOUTB3 (Note 6)

O

Buffered clock Bank B output (Note 8)

11

CLKOUTB4 (Note 6)

O

Buffered clock Bank B output (Note 8)

12

GND

P

Ground

13

VDD

P

3.3 V supply

14

CLKOUTA3 (Note 6)

O

Buffered clock Bank A output (Note 8)

15

CLKOUTA4 (Note 6)

O

Buffered clock Bank A output (Note 8)

16

DLY_CTRL (Note 6)

O

External Input−Output Delay control. This pin can be used as clock output.

5. Weak pull down

6. Weak pull−down on all outputs

7. Weak pull−up on these Inputs

8. Buffered clock output is Timing−Safe