Z86C9620VSC datasheet(12/46 Pages) ZILOG

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Z86C61/62/96

Z8® MICROCONTROLLER

PIN DESCRIPTION (Continued)

Table 6. Z86C96 68-Pin PLCC Pin Identification

Pin #

Symbol

Function

Direction

1-2

P44-P43

Port 4, Pins 3,4

In/Output

Power Supply

Input

P45

Port 4, Pin 5

In/Output

XTAL2

Crystal, Oscillator Clock

Output

XTAL1

Crystal, Oscillator Clock

Input

P37

Port 3, Pin 7

Output

P30

Port 3, Pin 0

Input

/RESET

Reset

Input

R//W

Read/Write

Output

/P0DS

Port 0 Data Strobe

Output

/DS

Data Strobe

Output

13-14

P47-P46

Port 4, Pins 6,7

In/Output

/P1DS

Port 1 Data Strobe

Output

/AS

Address Strobe

Output

/DTIMER

Disable Timers

Input

P35

Port 3, Pin 5

Output

N/C

Not Connected

Input

GND

Ground

Input

P32

Port 3, Pin 2

Input

22-23

P51-P50

Port 5, Pins 0,1

In/Output

PIN FUNCTIONS

XTAL1, XTAL2

Crystal 1, Crystal 2 (time-based input and

output, respectively). These pins connect a parallel-

resonant crystal, ceramic resonator, LC, or any external

single-phase clock to the on-chip oscillator and buffer.

R//W (output, write Low). The Read/Write signal is Low

when the MCU is writing to the external program or data

memory.

/RESET (input, active Low). To avoid asynchronous and

noisy reset problems, the Z86C61/62/96 is equipped with

a reset filter of four external clocks (4TpC). If the external

/RESET signal is less than 4TpC in duration, no reset

occurs.

On the fifth clock after the /RESET is detected, an internal

RST signal is latched and held for an internal register count

of 18 external clocks, or for the duration of the external

/RESET, whichever is longer. During the reset cycle, /DS is

held active Low while /AS cycles at a rate of TpC/2. When

/RESET is deactivated, program execution begins at loca-

tion 000C (HEX). Reset time must be held Low for 50 ms,

or until V

CC is stable, whichever is longer.

R//RL (input, active Low). This pin when connected to

GND disables the internal ROM and forces the device to

function as a Z86C96 ROMless Z8. (Note: When left

unconnected or pulled High to V

CC the part functions as a

normal Z86C61/62 ROM version.) This pin is only available

on the 44-pin version of the Z86C61, and both versions of

the Z86C62.

/DS (output, active Low). Data Strobe is activated once for

each external memory transfer. For a READ operation,

data must be available prior to the trailing edge of /DS. For

WRITE operations, the falling edge of /DS indicates that

output data is valid.

/AS (output, active Low). Address Strobe is pulsed once

at the beginning of each machine cycle. Address out-

put is through Port 1 for all external programs. Memory

address transfers are valid at the trailing edge of /AS.

Under program control, /AS can be placed in the high-

impedance state along with Ports 0 and 1, Data Strobe,

and Read/Write.

Pin #

Symbol

Function

Direction

24-31

P07-P00

Port 0, Pins 0,1,2,3,4,5,6,7 In/Output

Power Supply

Input

33-36

P55-P52

Port 5, Pins 2,3,4,5

In/Output

37-38

P11-P10

Port 1, Pins 0,1

In/Output

39-40

P57-P56

Port 5, Pins 6,7

In/Output

41-46

P17-P12

Port 1, Pins 2,3,4,5,6,7

In/Output

47-48

P63-P62

Port 6, Pins 3,2

In/Output

P34

Port 3, Pin 4

Output

P33

Port 3, Pin 3

Input

GND

Ground

Input

/SYNC

Synchronization

Output

SCLK

System Clock

Output

54-55

P21-P20

Port 2, Pins 0,1

In/Output

56-57

P61-P60

Port 6, Pins1,0

In/Output

58-63

P27-P22

Port 2, Pins 2,3,4,5,6,7

In/Output

64-65

P41-P40

Port 4, Pins 0,1

In/Output

P31

Port 3, Pin 1

Input

P36

Port 3, Pin 6

Output

P42

Port 4, Pin 2

In/Output

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