Z87100 datasheet(21/48 Pages) ZILOG

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Z87100

Zilog

Wireless Transmitter

DS96WRL0700

P R E L I M I N A R Y

3-21

In order to enter STOP (or HALT) mode, it is necessary to

first flush the instruction pipeline to avoid suspending exe-

cution in mid-instruction. To do this, the user executes a

NOP (opcode=FFH) immediately before the appropriate

sleep instruction; i.e.,

PN Modulator. The Z87100 incorporates a PN modulator

to allow generation of a direct sequence spread spectrum

data stream. Coupled with the appropriate transmitter cir-

cuitry, the Z87100 can support wireless and power line

spread spectrum transmission.

The PN modulator of the Z87100 is shown in Figure 15.

Major elements of the PN modulator include the PN ROM,

the PN modulator control logic, the data hold and data

shift registers, and the clock select multiplexor and PN and

data clock generator.

As part of the PN modulator, a specially designated area

of ROM (PN ROM) provides space for 256 bits (“chips”) of

one or more pseudorandom noise sequences. The PN

modulator control logic accesses the PN ROM as a circular

buffer and synchronously exclusive-or’s (XORs) each chip

of the sequence with the data bits loaded in the PN modu-

lator's data shift register, thereby PN modulating the data.

The PN code is accessed from the PN ROM beginning at

a specified relative address (PNADDR, register %02 in

bank C of the Expanded Register Group) until the chip cor-

responding to the PN code length (PNLEN, register %03 in

bank C of the Expanded Register Group) is reached, at

which point access continues again from the specified rel-

ative address.

The limits of the PN ROM address space are automatically

resolved by the control logic so that the PN ROM is effec-

tively a large circular buffer from which smaller circular

buffers defined by PNLEN and PNADDR can be access-

ed. Operation and control of the circular buffer is transpar-

ent to the user. As long as the sum of code lengths is less

than or equal to 256 chips, more than one PN sequence

may be ROM programmed, with the choice of code or even

a concatenation of codes to be used for transmission con-

trolled by Z8 software and the values of PNADDR and PN-

LEN.

Contents of PN ROM are shifted out and XOR’ed with the

contents of the data shift register. The rates at which the

two streams are shifted are controlled by the PN and data

clocks so that one or more PN chips are XOR’ed against a

single data bit, where the number of PN chips is deter-

mined by the value of PNLEN. The reference clock for the

PN modulator may be selected from the internal system

clock (SCLK) or either of the two counter/timers (T0 and

T1).

In nominal operation, the PN clock is defined by the select-

ed reference clock, and the data clock is then generated as

an integer fraction of the PN clock, where the integer is

specified by PNLEN. In this way, each data bit can be syn-

chronously modulated by a full PN code sequence as de-

fined by PNLEN, PNADDR, and the contents of PN ROM.

As a practical matter, this type of symbol-synchronous PN

modulation allows the corresponding spread spectrum re-

ceiver to be designed with improved acquisition perfor-

mance — since the PN and data modulation are synchro-

nously related at the transmitter, PN acquisition at the

receiver can simultaneously establish bit synchronization.

NOP; clear the pipeline

STOP; enter STOP mode

NOP; clear the pipeline

HALT; enter HALT mode

Z87100 Datasheet(PDF) 21 Page - Zilog, Inc.

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