Z87000 datasheet(21/50 Pages) ZILOG

21 / 50 page

Z87000/Z87L00

Zilog

Spread Spectrum Controllers

DS96WRL0501

P R E L I M I N A R Y

1-21

Receive 1-Bit ADC

The incoming receive signal at the RX analog input pin is

sampled by a 1-bit analog-to-digital converter at 8.192

MHz.

The receive signal is FSK-modulated (Frequency Shift

Keying) with a carrier frequency of 10.7 MHz (Intermediate

Frequency, or IF). The instantaneous frequency varies be-

tween 10.7 MHz plus or minus 32.58 kHz. Since the data

rate is 93.09 kbps, there are 88 samples per data bit. This

oversampled data is further processed by the demodulator

to retrieve the baseband information.

The 1-bit converter is implemented with a fast comparator,

which determines whether the RX signal is larger or small-

er than a reference signal (VREF). The Z87000 internally

generates the DC level of both VREF and RX input pins.

The received signal at 10.7 MHz should thus be AC cou-

pled to the RX pin via a coupling capacitor. To ensure ac-

curate operation of the converter, the user should also at-

tach to the VREF pin a network whose impedance

matches the DC impedance seen by the RX pin.

Demodulator

The demodulator includes a two-stage IF downconverter

that brings the sampled receive signal to baseband.

The narrow-band 10.7 MHz receive signal, sampled at

8.192 MHz by the 1-bit ADC, provides a 2.508 MHz useful

image. The first local oscillator used to downconvert this IF

signal is obtained from a Numerically Controlled Oscillator

(NCO) internal to the Z87000, at the nominal frequency of

460 kHz. The resulting signal is thus at 2.048 MHz (= 2.508

MHz - 460 kHz). A second downconversion by a 2.048

MHz signal brings the receive signal to baseband.

The exact frequency of the 460 kHz NCO is slightly adjust-

ed by the Automatic Frequency Control (AFC) loop for ex-

act downconversion of the end signal to the zero frequen-

cy. The AFC circuit detects any DC component in the

output of the limiter-discriminator (see below) when receiv-

ing a known sequence of data (preamble). This DC com-

ponent is called the “frequency bias”. The bias estimate

out of the AFC can be read by the DSP processor on every

frame and subsequently filtered. The processor then adds

or subtract this filtered bias to/from the NCO control word

to correct the NCO frequency output.

The main element of the demodulator is its limiter-discrim-

inator. The limiter-discriminator detects the frequency vari-

ations (ideally up to

± 32.58 kHz) and converts them to “0”

or “1” information bits. First, the data is processed through

low-pass filters to eliminate high frequency spurious com-

ponents introduced by the 1-bit ADC. The resulting signal

is then differentiated and fed to a matched filter. In the

matched filter, an integrate-and-dump operation is per-

formed to extract the digital information from its back-

ground noise.

The symbol clock is provided by the bit synchronizer. The

bit synchronizer circuit detects 0-to-1 and 1-to-0 transitions

in the incoming data stream in order to synchronize a dig-

ital phase-lock loop (DPLL). The PLL output is the recov-

ered bit clock, used to time the receiver on the base sta-

tion, and both receiver and transmitter on the handset.

To ensure enough transitions in the voice data stream, a

pseudo-random bit inversion operation is performed on the

outgoing voice data. The inversion is then reversed on the

demodulated data.

Figure 2. Demodulator Block Diagram

Rx signal

460 kHz

+ bias

1-bit

ADC

NCO

AFC

2.048 MHz

Filter

Limiter-

Discriminator

SNR

Bit

Sync

Frame

Sync

Buffer

SSB

Z87000 Datasheet(PDF) 21 Page - Zilog, Inc.

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