AS4LC8M8S0 datasheet(3/24 Pages) ALSC

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AS4LC8M8S0

AS4LC4M16S0

7/5/00

ALLIANCE SEMICONDUCTOR

Pin descriptions

Name

Description

CLK

System clock

All operations synchronized to rising edge of CLK. It also increments

the burst counters.

CKE

Clock enable

Controls CLK input. If CKE is high, the next CLK rising edge is valid.

If CKE is low, the internal clock is suspended from the next clock

cycle and the burst address and output states are frozen. Pulling CKE

low has the following effects:

all banks idle: Precharge power down and Self refresh.

row active in any bank: Active power down.

burst/access in progress: Clock suspend.

When in Power down or Self refresh mode, CKE becomes

asynchronous until exiting the mode.

Chip select

Enables or disables device operation by masking or enabling all inputs

except CLK, CKE, UDQM/LDQM (

×16), DQM (×8).

A0~A11

Address

Row and column addresses are multiplexed. Row address: A0~A11.

Column address (8M

×8): A0~A8. Column address (4M×16):

A0~A7.

BA0, BA1

Bank select

Memory cell array is organized in 4 banks. BA0 and BA1 select which

internal bank will be active during activate, read, write, and

precharge operations.

RAS

Row address strobe

Enables row access and precharge operation. When RAS is low, row

address is latched at the rising edge of CLK.

CAS

Column address strobe

Enables column access. When CAS is low, starting column address for

the burst access operation is latched at the rising edge of the CLK.

Write enable

Enables write operation and row precharge operation.

×8: DQM

×16: UDQM/LDQM

Output disable/ write

mask

Controls I/O buffers. When DQM is high, output buffers are disabled

during a read operation and input data is masked during a write

operation. DQM latency is 2 clocks for Read and 0 clocks for Write.

For

×16, LDQM controls lower byte (DQ0–7) and UDQM controls

upper byte (DQ8–15). For

×8, only one DQM controls the 8 DQs.

UDQM and LDQM are considered same state when referenced as

DQM.

DQ0~DQ15

Data input/output

Data inputs/outputs are multiplexed. Data bus for 8M

×8 is

DQ0~DQ7 only.

VDD/VSS

Power supply/ground Power and ground for core logic and input buffers.

VDDQ/VSSQ

Data output power/

ground

Power and ground for data output buffers.

AS4LC8M8S0 Datasheet(PDF) 3 Page - Alliance Semiconductor Corporation

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