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AS8202B

Datasheet - Detailed Descr i p ti on

7.2 Reset and Oscillator

7.2.1 External Reset Signal

To issue a reset of the chip the RESETB port has to be driven low for at least 1µs. Pulses under 50ns duration are discarded. At power-up the

reset must overlap the build-up time of the power supply. This reset may only be used if a proper power-on reset can be ensured (refer to Section

7.2.2 Integrated Power-On Reset).

7.2.2 Integrated Power-On Reset

The device has an internal Power-On-Reset generator. When supply voltage ramps up, the internal reset signal is kept active (low) for 33µs

typical.

Note: In case of non-compliance keep the external reset (RESETB) active for min. 5 ms after supply voltage is valid and main clock is stable.

7.2.3 Oscillator Circuitry

The main clock requires an external oscillator. The bus guardian requires an external oscillator or an external quartz.

Figure 9. Main Clock Setup

XIN0 of the main clock shall be supplied by a 40MHz clock provided by an oscillator IC.

Table 6. Pin Mode

Pin Name

Mode

Comment

XIN1

analog

Bus guardian oscillator input (external clock input)

RESETB

in

External reset

Table 7. Parameters

Symbol

Parameter

Min

Typ

Max

Unit

dV/dt

supply voltage slope

551

-

-

V/ms

tpores

power on reset active time after VDD > 1,0V

25

33

49

µs

External oscillator

40MHz

square

wave