CLK

G

N

Y

N

CDCVF2310

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SCAS666D – JUNE 2001 – REVISED OCTOBER 2015

Typical Application (continued)

9.2.3 Application Curves

Figure 9. CDCVF2310 Output Phase Noise 169.6 fs

Figure 8. CDCVF2310 Output Phase Noise 89.1 fs

(12kHz to 5MHz), Reference Phase Noise 161.5 fs,

(12 kHz to 20 MHz), Reference Phase Noise 76.9 fs, Output

Frequency 30.72 MHz

Frequency 125 MHz

The low-additive jitter of the CDCVF2310 can be seen in the previous application plots. The low-noise, 125-MHz

input source drives the CDCVF2310, resulting in 45-fs RMS additive jitter when integrated from 12 kHz to 20

MHz for this configuration. The low-noise 30.72-MHz input source drives the CDCVF2310, resulting in 52-fs RMS

additive jitter when integrated from 12 kHz to 5 MHz for this configuration.

Figure 10. CDCVF2310 Configured as Gate Function for Output Clock

Suppression Circuit for required timings.

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