TS3003 datasheet(3/11 Pages) SILABS

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TS3003

TS3003 Rev. 1.0

Page 3

ELECTRICAL CHARACTERISTICS

VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF, CLOAD(PWM) = 0pF, CPWM = 47pF, unless otherwise

noted. Values are at TA = 25°C unless otherwise noted. See Note 1.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

VDD

1.55

5.25

Supply Current

IDD

CPWM = VDD

1.9

2.4

µA

-40°C

≤ T

A ≤ 85°C

2.7

3.3

3.6

-40°C

≤ T

A ≤ 85°C

4.5

FOUT Period

tFOUT

40.1

41.2

µs

-40°C

≤ T

A ≤ 85°C

FOUT Period Line

Regulation

∆t

FOUT/V

1.55V

≤ V

DD ≤ 5.25V

0.17

%/V

FOUT Duty cycle

FOUT Period

Temperature

Coefficient

∆t

FOUT/∆T

0.02

%/°C

PWMOUT Duty Cycle

DC(PWMOUT)

41.6

VPWM_CNTRL= 0V

PWMOUT Duty Cycle

Line Regulation

ΔDC(PWMOUT)/V

1.55V < VDD < 5.25V, FDIV2:0 = 000

-3

CPWM Sourcing Current

ICPWM

930

1050

-40°C

≤ T

A ≤ 85°C

810

1150

UVLO Hysteresis

VUVLO

(VDD=1.55V) – (VDD_SHUTDOWN VOLTAGE)

150

250

FOUT, PWMOUT

Rise Time

tRISE

See Note 2, CL = 15pF

FOUT, PWMOUT

Fall Time

tFALL

See Note 2, CL = 15pF

FOUT Jitter

See Note 3

0.001

RSET Pin Voltage

V(RSET)

0.3

FDIV Input Current

IFDIV

-40°C

≤ T

A ≤ 85°C

Maximum Oscillator

Frequency

Fosc

RSET= 360K

300

kHz

High Level Output

Voltage, FOUT and

PWMOUT

VDD - VOH

IOH = 1mA

160

Low Level Output

Voltage, FOUT and

PWMOUT

VOL

IOL = 1mA

140

Dead Time

TDT

FOUT edge falling and PWMOUT edge rising

106

Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified.

Note 2: Output rise and fall times are measured between the 10% and 90% of the VDD power-supply voltage levels. The specification is based

on lab bench characterization and is not tested in production.

Note 3: Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench

characterization and is not tested in production.

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