LAN9354 datasheet(21/487 Pages) MICROCHIP

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DS00001926B-page 21

LAN9354

TABLE 3-7:

EEPROM PIN DESCRIPTIONS

Num

Pins

Name

Symbol

Buffer

Type

Description

EEPROM I2C

Serial Data

Input/Output

EESDA

VIS/VOD8

When the device is accessing an external EEPROM

this pin is the I2C serial data input/open-drain out-

put.

Note:

This pin must be pulled-up by an exter-

nal resistor at all times.

EEPROM I2C

Serial Clock

EESCL

VIS/VOD8

When the device is accessing an external EEPROM

this pin is the I2C clock input/open-drain output.

Note:

This pin must be pulled-up by an exter-

nal resistor at all times.

TABLE 3-8:

GPIO, LED & CONFIGURATION STRAP PIN DESCRIPTIONS

Num

Pins

Name

Symbol

Buffer

Type

Description

General

Purpose I/O 7

GPIO7

VIS/VO12/

VOD12

(PU)

This pin is configured to operate as a GPIO. The pin

is fully programmable as either a push-pull output,

an open-drain output or a Schmitt-triggered input by

writing the General Purpose I/O Configuration Reg-

ister (GPIO_CFG) and the General Purpose I/O

Data & Direction Register (GPIO_DATA_DIR).

General

Purpose I/O 6

GPIO6

VIS/VO12/

VOD12

(PU)

This pin is configured to operate as a GPIO. The pin

is fully programmable as either a push-pull output,

an open-drain output or a Schmitt-triggered input by

writing the General Purpose I/O Configuration Reg-

ister (GPIO_CFG) and the General Purpose I/O

Data & Direction Register (GPIO_DATA_DIR).

LED 5

LED5

VO12/

VOD12/

VOS12

This pin is configured to operate as an LED when

the LED 5 Enable bit of the LED Configuration Reg-

ister (LED_CFG) is set. The buffer type depends on

the setting of the LED Function 2-0 (LED_FUN[2:0])

field in the LED Configuration Register (LED_CFG)

and is configured to be either a push-pull or open-

drain/open-source output. When selected as an

open-drain/open-source output, the polarity of this

pin depends upon the PHYADD strap value sam-

pled at reset.

Note:

Refer to Section 17.3, "LED Operation,"

on page 452 to additional information.

General

Purpose I/O 5

GPIO5

VIS/VO12/

VOD12

(PU)

This pin is configured to operate as a GPIO when

the LED 5 Enable bit of the LED Configuration Reg-

ister (LED_CFG) is clear. The pin is fully program-

mable as either a push-pull output, an open-drain

output or a Schmitt-triggered input by writing the

General Purpose I/O Configuration Register (GPI-

O_CFG) and the General Purpose I/O Data & Direc-

tion Register (GPIO_DATA_DIR).

PHY Address

Configuration

Strap

PHYADD

VIS

(PU)

This strap configures the default value of the Switch

PHY Address Select soft-strap. See Note 9.

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