LNBH25SPQR datasheet(23/37 Pages) STMICROELECTRONICS

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LNBH25S

I²C interface protocol

DocID026736 Rev 2

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The writing procedure can start from any register address (status 1,2 or data 1..4)

by simply setting X values in the register address byte (after the chip address). It

can be also stopped by the master by sending a stop condition after any

acknowledge bit.

7.3

Data registers

The data 1..4 registers can be addressed both to write and read mode. In read mode they

return the last writing byte status received in the previous write transmission.

The following tables provide the register address values of data 1..4 and a function

description of each bit.

Table 7: Data 1 (read/write register. Register address = 0X2)

Bit

Name

Value

Description

Bit 0

(LSB)

VSEL1

0/1

Output voltage selection bits. Refer to Table 14: "Output voltage

selection table (data1 register, write mode)"

Bit 1

VSEL2

0/1

Bit 2

VSEL3

0/1

Bit 3

VSEL4

0/1

Bit 4

N/A

Reserved. Keep to “0”

Bit 5

N/A

Reserved. Keep to “0”

Bit 6

N/A

Reserved. Keep to “0”

Bit 7

(MSB)

N/A

Reserved. Keep to “0”

N/A = reserved bit

All bits reset to “0” at power-on

Table 8: Data 2 (read/write register. Register address = 0X3)

Bit

Name

Value

Description

Bit 0 (LSB)

TEN

22 kHz tone enabled. Tone output controlled by DSQIN pin

22 kHz tone output disabled

Bit 1

LPM

Low power mode active (used with 22 kHz tone output

disabled only)

Low power mode deactivated (keep always LPM = 0

during 22 kHz tone transmission)

Bit 2

EXTM

DSQIN input pin is set to receive external 22 kHz TTL

signal source

DSQIN input pin is set to receive external DiSEqC

envelope TTL signal

Bit 3

N/A

Reserved. Keep to “0”

Bit 4

N/A

Reserved. Keep to “0”

Bit 5

N/A

Reserved. Keep to “0”

Bit 6

N/A

Reserved. Keep to “0”

Bit 7(MSB)

N/A

Reserved. Keep to “0”

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