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DP83867CSRGZR Datasheet(PDF) 29 Page - Texas Instruments

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Part # DP83867CSRGZR
Description  High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver
PDF  114 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DP83867CSRGZR Datasheet(HTML) 29 Page - Texas Instruments

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DP83867CS, DP83867IS, DP83867E
www.ti.com
SNLS504 – OCTOBER 2015
9.4.3.4 Next Page Support
The DP83867 supports the Auto-Negotiation Next Page protocol as required by IEEE 802.3 clause 28.2.4.1.7.
The ANNPTR 0x07 allows for the configuration and transmission of the Next Page. Refer to clause 28 of the
IEEE 802.3 standard for detailed information regarding the Auto-Negotiation Next Page function.
9.4.3.5 Parallel Detection
The DP83867 supports the Parallel Detection function as defined in the IEEE 802.3 specification. Parallel
Detection requires the 10/100 Mbps receivers to monitor the receive signal and report link status to the Auto-
Negotiation function. Auto-Negotiation uses this information to configure the correct technology in the event that
the Link Partner does not support Auto-Negotiation, yet is transmitting link signals that the 10BASE-Te or
100BASE-X PMA recognize as valid link signals.
If the DP83867 completes Auto-Negotiation as a result of Parallel Detection, without Next Page operation, bits 5
and 7 of ANLPAR (register address 0x0005) will be set to reflect the mode of operation present in the Link
Partner. Note that bits 4:0 of the ANLPAR will also be set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may determine that the negotiation is completed via Parallel
Detection by reading ‘0’ in bit 0 of ANER (register address 0x006) after Auto-Negotiation Complete, bit 5 of
BMSR (register address 0x0001), is set. If the PHY is configured for parallel detect mode and any condition other
than a good link occurs, the parallel detect fault, bit 4 of ANER (register address 0x06), will set.
9.4.3.6 Restart Auto-Negotiation
If a link is established by successful Auto-Negotiation and then lost, the Auto-Negotiation process will resume to
determine the configuration for the link. This function ensures that a link can be re-established if the cable
becomes disconnected and re-connected. After Auto-Negotiation is completed, it may be restarted at any time by
writing ‘1’ to bit 9 of the BMCR (register address 0x0000). A restart Auto-Negotiation request from any entity,
such as a management agent, will cause DP83867 to halt data transmission or link pulse activity until the
break_link_timer expires. Consequently, the Link Partner will go into link fail mode and the resume Auto-
Negotiation. The DP83867 will resume Auto-Negotiation after the break_link_timer has expired by transmitting
FLP (Fast Link Pulse) bursts.
9.4.3.7 Enabling Auto-Negotiation via Software
If the DP83867 is initialized upon power-up with Auto-Negotiation disabled and the user may desire to restart
Auto-Negotiation, this could be accomplished by software access. Bit 12 of BMCR (register address 0x00) should
be cleared and then set for Auto-Negotiation operation to take place.
9.4.3.8 Auto-Negotiation Complete Time
Parallel detection and Auto-Negotiation typically take 2-3 seconds to complete. In addition, Auto-Negotiation with
next page exchange takes approximately 2-3 seconds to complete, depending on the number of next pages
exchanged. Refer to Clause 28 of the IEEE 802.3 standard for a full description of the individual timers related to
Auto-Negotiation
9.4.3.9 Auto-MDIX Resolution
The DP83867 can determine if a “straight” or “crossover” cable is used to connect to the link partner. It can
automatically re-assign channel A and B to establish link with the link partner, (and channel C and D in
1000BASE-T mode). Auto-MDIX resolution precedes the actual Auto-Negotiation process that involves exchange
of FLPs to advertise capabilities. Automatic MDI/MDIX is described in IEEE 802.3 Clause 40, section 40.8.2. It is
not a required implementation for 10BASE-Te and 100BASE-TX.
Auto-MDIX can be enabled or disabled by strap, using the AMDIX Disable strap, or by register configuration,
using bit 6 of the PHYCR register (address 0x0010). When Auto-MDIX is disabled, the PMA is forced to either
MDI (“straight”) or MDIX (“crossed”). Manual configuration of MDI or MDIX can also be accomplished by strap,
using the Force MDI/X strap, or by register configuration, using bit 5 of the PHYCR register.
For 10/100, Auto-MDIX is independent of Auto-Negotiation. Auto-MDIX works in both Auto-Negotiation mode and
manual forced speed mode.
Copyright © 2015, Texas Instruments Incorporated
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