M24C08-DRMN3TP datasheet(12/39 Pages) STMICROELECTRONICS

12 / 39 page

Device operation

M24C08-A125

12/39

DocID025850 Rev 5

3.5

Device addressing

To start communication between the bus master and the slave device, the bus master must

initiate a Start condition. Following this, the bus master sends the device select code, as

shown in Table 2.

The device select code consists of a 4-bit device type identifier and a Chip Enable address

(E2). A device select code handling any value other than 1010b (to select the memory) or

1011b (to select the Identification page) is not acknowledged by the memory device.

Up to two memory devices can be connected on a single I2C bus. When the device select

code is received, the memory device only responds if the Chip Enable Address is the same

as the value decoded on the E2 input.

The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write

operations.

If the memory device does not match the device select code, it deselects itself from the bus,

and enters the Standby mode.

If the memory device matches the device select code, the corresponding memory device

gives an acknowledgment on Serial Data (SDA) during the 9th SCL clock period. Once the

memory device has acknowledged the device select code, the memory device waits for the

master to send the address byte. The memory device responds to the address byte with an

acknowledge bit.

Table 2. Device select code

Device type identifier (1)

1. The most significant bit, b7, is sent first.

Chip Enable address(2)

2. X bit is a Don’t Care bit

When accessing the

memory

1010

When accessing the

identification page

1011

M24C08-DRMN3TP Datasheet(PDF) 12 Page - STMicroelectronics