M24M01-DWMN3TP datasheet(12/37 Pages) STMICROELECTRONICS

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Device operation

M24M01-A125

12/37

DocID023765 Rev 4

3.5

Device addressing

To start communication between the bus master and the slave device, the bus master must

initiate a Start condition. Following this, the bus master sends the device select code, as

shown in Table 2.

The device select code consists of a 4-bit device type identifier and a 2-bit Chip Enable

address (E2, E1). A device select code handling any value other than 1010b (to select the

memory) or 1011b (to select the Identification page) is not acknowledged by the memory

device.

Up to four memory devices can be connected on a single I2C bus. Each one is given a

unique 2-bit code on the Chip Enable (E2, E1) inputs. When the device select code is

received, the memory device only responds if the Chip Enable Address is the same as the

value decoded on the E2, E1 inputs.

The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.

If a match occurs on the device select code, the corresponding memory device gives an

acknowledgment on Serial Data (SDA) during the 9th bit time. If the memory device does not

match the device select code, it deselects itself from the bus, and goes into Standby mode.

Once the memory device has acknowledged the device select code (Table 2), the memory

device waits for the master to send two address bytes (most significant address byte sent

first, followed by the least significant address byte (Table 3). The memory device responds

to each address byte with an acknowledge bit.

Note:

A: significant address bit.

X: bit is Don’t Care.

Table 2. Device select code

Device type identifier(1)

1. The most significant bit, b7, is sent first.

Chip Enable

address(2)

2. E2 and E1 bits are compared with the value read on input pins E2,E1.

Address

bit

When accessing

the memory

A16

When accessing

the Identification

page

X(3)

3. X = don’t care.

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