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M93Cx6-DRE

READY/BUSY status

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READY/BUSY status

While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL

instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.

becomes available). In this state, the M93Cx6-DRE ignores any data on the bus. When the

Write cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)

indicates that the M93Cx6-DRE is ready to receive the next instruction. Serial Data Output

(Q) remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is

decoded.

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Initial delivery state

The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).

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Common I/O operation

Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a

current limiting resistor, to form a common, single-wire data bus. Some precautions must be

taken when operating the memory in this way, mostly to prevent a short circuit current from

flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output

(Q). Please see the application note AN394 for details.