M24128S-FCU datasheet(39/40 Pages) STMICROELECTRONICS

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M24128S-FCU M24128S-FCV

Revision history

Table 17. Document revision history

Date

Revision

Changes

07-Jan-2014

Initial release.

26-May-2014

Changed document classification from “ST Restricted” to “Public”.

Added Figure 12: Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer

level chip scale package outline.

18-Jun-2014

Changed minimum level of temperature range from -30°C to -40°C on

Cover page, Section 1, Table 12 and Table 16

Changed minimum level of supply voltage range from 1.62 V to 1.7V on

Cover page, Section 1, Table 12 and Table 16

11-Dec-2014

Updated Features

Updated Table 8: Operating conditions

Added Figure 10: Maximum Rbus value versus bus parasitic

capacitance (Cbus) for an I2C bus at high clock frequency

Added Figure 13: Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer

level chip scale package outline with BSC

Added Figure 14: Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level

chip scale package recommended footprint

Added Table 11: High frequency clock AC characteristics.

Updated Table 12: Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm,

wafer level chip scale package mechanical data

Added Table 13: Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer

level chip scale package mechanical data

Added option F inside Table 16: Ordering information scheme

30-Apr-2015

Change from Preliminary to Production data status

Updated Icc(read) value in Table 9: DC characteristics

Updated Figure 9: Maximum Rbus value versus bus parasitic

capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz

12-Aug-2015

Updated:

– Data retention value from 40 to 200 years and Cycling from 1 to 4

Mcycles in Cover page and Table 7.

05-Nov-2015

Added:

– reference to M24128S-FCV device.

– Note 1 on Table 11.

– Notes 1 and 2 on Table 16

– Section 9.2: Ultra ultra thin WLCSP package information

Updated:

– Figure 1, Figure 4.

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