M95320-DRMF8TP datasheet(13/41 Pages) STMICROELECTRONICS

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M95320-DRE

Operating features

SRWD bit and W input signal

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect pin (W) signal. When the SRWD bit is written to 0, it is possible to write the Status

When the SRWD bit is written to 1, two cases have to be considered, depending on the

state of the W input pin:

•

Case 1: if pin W is driven high, it is possible to write the Status Register.

•

Case 2: if pin W is driven low, it is not possible to write the Status Register (WRSR is

discarded) and therefore SRWD,BP1,BP0 bits cannot be changed (the size of the

protected memory block defined by BP1,BP0 bits is frozen).

Case 2 can be entered in either sequence:

•

Writing SRWD bit to 1 after driving pin W low, or

•

Driving pin W low after writing SRWD bit to 1.

The only way to exit Case 2 is to pull pin W high.

Note: if pin W is permanently tied high, the Status Register cannot be write-protected.

The protection features of the device are summarized in Table 4.

3.5

Identification page

The M95320-DRE offers an Identification page (32 bytes) in addition to the 32 Kbit memory.

The Identification page contains two fields:

•

Device identification: the three first bytes are programmed by STMicroelectronics with

the Device identification code, as shown in Table 5.

•

Application parameters: the bytes after the Device identification code are available for

application specific data.

Table 3. Write-protected block size

Status Register bits

Protected block

Protected array addresses

BP1

BP0

None

Upper quarter

0C00h - 0FFFh

Upper half

0800h - 0FFFh

Whole memory

0000h - 0FFFh plus Identification page

Table 4. Protection modes

SRWD bit

W signal

Status

Status Register is writable.

Status Register is write-protected.

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