SAFC161K datasheet(41/66 Pages) INFINEON

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C161K

C161O

Data Sheet

V2.0, 2001-01

Prescaler Operation

When prescaler operation is configured (CLKCFG = 1XXB) the CPU clock is derived

from the internal oscillator (input clock signal) by a 2:1 prescaler.

The frequency of

fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e.

the duration of an individual TCL) is defined by the period of the input clock

fOSC.

The timings listed in the AC Characteristics that refer to TCLs therefore can be

calculated using the period of

fOSC for any TCL.

Direct Drive

When direct drive is configured (CLKCFG = 0XXB) the CPU clock is directly driven from

the internal oscillator with the input clock signal.

The frequency of

fCPU directly follows the frequency of fOSC so the high and low time of

fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock

fOSC.

The timings listed below that refer to TCLs therefore must be calculated using the

minimum TCL that is possible under the respective circumstances. This minimum value

can be calculated via the following formula:

TCLmin = 1/fOSC × DCmin

(DC = duty cycle)

For two consecutive TCLs the deviation caused by the duty cycle of

fOSC is compensated

so the duration of 2TCL is always 1/

fOSC. The minimum value TCLmin therefore has to

be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that

require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/

fOSC.

Table 9

C161K/O Clock Generation Modes

CLKCFG

(P0H.7-5)

CPU Frequency

fCPU = fOSC × F

External Clock

Input Range

Notes

0X X

fOSC × 1

1 to 25 MHz

Direct drive1)

1X X

fOSC / 2

2 to 50 MHz

CPU clock via prescaler

1) The maximum frequency depends on the duty cycle of the external clock signal.

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