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STM32F756VG Datasheet(PDF) 19 Page - STMicroelectronics |
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STM32F756VG Datasheet(HTML) 19 Page - STMicroelectronics |
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19 / 228 page  DocID027589 Rev 4 19/228 STM32F756xx Functional overview 45 Figure 3. STM32F756xx AXI-AHB bus matrix architecture 1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus. 2.7 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. |
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