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I3G4250D Datasheet(PDF) 20 Page - STMicroelectronics |
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I3G4250D Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 43 page  Application hints I3G4250D 20/43 DocID027628 Rev 2 4 Application hints Figure 11. I3G4250D electrical connections and external component values Power supply decoupling capacitors (100 nF ceramic or polyester +10 μF) should be placed as near as possible to the device (common design practice). If Vdd and Vdd_IO are not connected together, power supply decoupling capacitors (100 nF and 10 μF between Vdd and common ground, 100 nF between Vdd_IO and common ground) should be placed as near as possible to the device (common design practice). The I3G4250D IC includes a PLL (phase-locked loop) circuit to synchronize driving and sensing interfaces. Capacitors and resistors must be connected to the PLLFILT pin (as shown in Figure 11) to implement a second-order low-pass filter. Table 10 summarizes the PLL low-pass filter component values. Table 10. PLL low-pass filter component values Component Value C1 10 nF ± 10% C2 470 nF ± 10% R2 10 k ± 10% |
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