PAC5250 datasheet(39/70 Pages) ACTIVE-SEMI

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PAC5250

Power Application Controller

Table 21. Power Driver Resources by Part Number

PART

NUMBER

LOW-SIDE GATE

DRIVER

HIGH-SIDE GATE DRIVER

OPEN-DRAIN DRIVER

DRLx

SOURCE /

SINK

CURRENT

DXHx

MAX

SUPPLY

SOURCE/

SINK

CURRENT

OMx

PAC5250

1A/1A

600V

0.25A/0.5A

2 (23V/ 40mA)

The ASPD includes built-in configurable fault protection for the internal gate drivers. On PAC5250, the protection signal

ENHS2 are provided for external circuitry driver fault protection.

12.3.1. Low-Side Gate Driver

The DRLx low-side gate driver drives the gate of an external MOSFET or IGBT switch between the low-level VSSP power

ground rail and high-level VP supply rail. The DRLx output pin has sink and source output current capability of 1A. Each

low-side gate driver is controlled by a microcontroller port signal with 4 configurable levels of propagation delay.

12.3.2. Ultra-High-Voltage Gate Driver

The DXHx ultra-high-voltage high-side gate driver drives the gate of an external MOSFET or IGBT switch between its

low-level DXSx driver source rail and its high-level DXBx bootstrap rail. The DXSx pin can go up to 600V. The DXHx

output pin has 0.5A sink and 0.25A source output current capability. The DXBx bootstrap pin can have a maximum

operating voltage of 20V relative to the DXSx pin. The DXSx pin is designed to tolerate momentary switching negative

spikes down to -10V without affecting the DXHx output state. Each ultra-high-voltage high-side gate driver is controlled by

a microcontroller port signal.

For bootstrapped high-side operation, connect an appropriate capacitor between DXBx and DXSx and a properly rated

bootstrap diode from VP rail to DXBx.

12.3.3. High-Side Switching Transients

Typical high-side switching transients are shown in Figure 12-3(a). To ensure functionality and reliability, the DXSx and

DXBx pins must not exceed the peak and undershoot limit values shown. This should be verified by probing the DXSx and

DXBx pins directly relative to VSS pin. A small resistor and diode clamp for the DXSx pin can be used to make sure that

the pin voltage stays within the negative limit value. In addition, the high-side slew rate dV/dt must be kept within ±50V/ns

for DXSx. This can be achieved by adding a resistor-diode pair in series, and an optional capacitor in parallel with the

power switch gate. The parallel capacitor also provides a low impedance and close gate shunt against coupling from the

switch drain. These optional protection and slew rate control are shown in Figure 12-3(b).

- 39 -

Rev 1.6‒January 28, 2016

Figure 12-2. Typical Gate Driver Connections

DXHx

DRLx

DXSx

DXBx

PAC5250

(To loads/inductors.)

PAC5250 Datasheet(PDF) 39 Page - Active-Semi, Inc

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