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DRV8302

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SLES267C – AUGUST 2011 – REVISED MARCH 2016

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Copyright © 2011–2016, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 Three-Phase Gate Driver

The half-bridge drivers use a bootstrap configuration with a trickle charge pump to support 100% duty cycle

operation. Each half-bridge is configured to drive two N-channel MOSFETs, one for the high-side and one for the

low-side. The half-bridge drivers can be used in combination to drive a 3-phase motor or separately to drive

various other loads.

The internal dead times are adjustable to accommodate a variety of external MOSFETs and applications. The

dead time is adjusted with an external resistor on the DTC pin. Shorting the DTC pin to ground provides the

minimum dead time (50 ns). There is an internal hand shake between the high side and low side MOSFETs

during switching transitions to prevent current shoot-through.

The three-phase gate driver can provide up to 30 mA of average gate driver current. This can support switching

frequencies up to 200 kHz when the MOSFET Qg = 25 nC. The high side gate drive will survive negative output

from the half-bridge up to –10 V for 10 ns. During EN_GATE low and fault conditions the gate driver keeps the

external MOSFETs in high impedance mode.

voltage from the drain to the source of the external MOSFETs while the MOSFET is enabled. This voltage is

compared against the programmed trip point to determine if an overcurrent event has occurred. The trip voltage

is set through the OC_ADJ pin with a voltage usually set with a resistor divider. The high-side sense is between

the PVDD1 and SH_X pins. The low-side sense is between the SH_X and SL_X pins. Ensuring a differential, low

impedance connection to the external MOSFETs for these lines helps provide accurate VDS sensing. The

DRV8302 provides both cycle-by-cycle current limiting and latch overcurrent shutdown of the external MOSFET

through the M_OC pin.

The DRV8302 allows for both 6-PWM and 3-PWM control through the M_PWM pin.

Table 1. 6-PWM Mode

INL_X

INH_X

GL_X

GH_X

0

0

L

L

0

1

L

H

1

0

H

L

1

1

L

L

Table 2. 3-PWM Mode

INL_X

INH_X

GL_X

GH_X

X

0

H

L

X

1

L

H

(1)

Table 3. Gate Driver External Components

NAME

PIN 1

PIN 2

RECOMMENDED

nOCTW

(1)

≥10 kΩ

nFAULT

(1)

≥10 kΩ

DTC

GND (PowerPAD)

0 to 150 k

Ω (50 ns to 500 ns)

GVDD

GND (PowerPAD)

2.2 µF (20%) ceramic,

≥ 16 V

CP1

CP2

0.022 µF (20%) ceramic, rated for PVDD1

DVDD

AGND

1 µF (20%) ceramic,

≥ 6.3 V

AVDD

AGND

1 µF (20%) ceramic,

≥ 10 V

PVDD1

GND (PowerPAD)

≥4.7 µF (20%) ceramic, rated for PVDD1

BST_X

SH_X

0.1 µF (20%) ceramic,

≥ 16 V