Data Sheet

3

V 2.2, 2004-03-09

AEB02800_13

Chopped

Amplifier

Hall

Probe

Latch

Active Error

Compensation

Oscillator

&

Sequencer

Threshold

Generator

Bias and

Compensation

Circuits

V

S

1

3

GND

Comparator

with

Hysteresis

2 Q

Decision

Logic

Figure 2 Block Diagram

Circuit Description

The Low Power Hall IC Switch comprises a Hall probe, bias generator, compensation

circuits, oscillator, output latch and an n-channel open drain output transistor.

The bias generator provides currents for the Hall probe and the active circuits.

Compensation circuits stabilize the temperature behavior and reduce technology variations.

The Active Error Compensation rejects offsets in signal stages and the influence of

mechanical stress to the Hall probe caused by molding and soldering processes and other

thermal stresses in the package. This chopper technique together with the threshold

generator and the comparator ensures high accurate magnetic switching points.

Very low power consumption is achieved with a timing scheme controlled by an oscillator

and a sequencer. This circuitry activates the sensor for 50 µs (typical operating time) sets

the output state after sequential questioning of the switch points and latches it with the

beginning of the following standby phase (max. 200 ms). In the standby phase the average

current is reduced to typical 4 µA. Because of the long standby time compared to the

operating time the overall averaged current is only slightly higher than the standby current.