Aeroflex Colorado Springs Application Note

AN-MEM-002

Creation Date: 8/19/11

Page 4 of 5

Modification Date: 4/24/13

3.1 Simultaneous Control and Address Switching

Simultaneous switching of controls and address pins, alone, is not a problem; excessive skew between them is the concern.

Consider the application where several SRAM devices are connected to the same memory bus. The address bus is commonly

connected to all the devices, but the chip enable pin is singularly connected to each individual SRAM. This configuration

results in a loading difference between the address inputs and the chip enable. This lightly loaded chip enable propagates to the

memory more quickly than the heavily loaded address lines. The oscilloscope capture of Figure #1 is the actual timing of an

application which had intermittent data errors due to address transitions lagging chip enable.

Figure #1 SRAM Signal Capture

The signal transitions in the scope plot of Figure #1 appear to be fairly coincidental. A closer look however, reveals the chip

(closer to actual logical gate switching of the inputs), the delta in signal times is still approximately 6ns.

Simultaneous switching of controls and address inputs is not recommended for a couple of reasons. The first is the previously

described signal skew sensitivity between controls and/or address inputs. The second reason is that activating all the controls

and address inputs simultaneously results in peak instantaneous current consumption. This condition causes maximum strain

to the power decoupling. Chip Enable activates address decoding circuits, address switching introduces input buffer switching

current, and output enable assertion turns on all the device output drivers. Peforming all three simultaneously results in worst

case transient current demand by the memory.

3.1.0 Technical Overview of Skew Sensitivity

Recall from section 2.0 that any activity requesting new data causes a read trigger. The triggers are wire-ORed together. In

order to meet the faster access times demanded by today’s applications, the ORed trigger only exists during the first 4-5ns of

the read cycle. Since the slowest of the address transitions occurs more than 5ns after the initiation of the read activity, a sec-

ond read activity is initiated. The sensing circuit does not have time to normalize before the second read activity has started.

For this reason a Chip Enable-Controlled read cycle requires that address inputs remain stable for the entire cycle. Infrequent

and random sensing errors can result if the bit columns are continually pulled to one state then quickly requested to sense the

opposite state. Another effect of the low power read architecture that differs from previous generation designs (those that con-

tinually sense for data) is that the bit line will not be sensed again until another read triggering event occurs. If another read

trigger event (chip enable assertion and/or address change) does no occur for a particular address, the incorrect data remains at

the outputs.



Timing shown from VIL (yellow trace /CS) and VIH (pink for address signal) as delta X =

6ns. Even at actual internal gate switching point (~ VDD/2), the skew is still around 6ns.

Chip Enable (/E)

Address Signal (Ax)