2

PIN DESCRIPTIONS

Number

Pins

Type

Description

1MR

Digital Input

TTL/CMOS

compatible

Manual Reset Input with an internal pull-up. Active low. MR low forces the reset

output RESET_OD low. Required minimum MR pulse width is 150ns. RESET_OD

is held low for duration of the reset timer.

2VDD

Supply

internally by a dedicated comparator circuit, which employs an internal bandgap

voltage, nominally 4.65V, RESET_OD and WDO outputs are forced low. (See WDO

and RESET_OD descriptions.) (Figure 4.)

3GND

Supply

ASIC Ground. This pin should be tied to ground and establishes the reference for

voltage detection.

4

PFI

Analog Input

Threshold detector input. Voltage on this input is fed directly to an internal

comparator where it is compared to the bandgap voltage reference of 1.25vV It can

be used for detection of low battery or power failure of voltage supplies other than

is forced low, otherwise, stays high.

5PFO

Digital Output

Threshold detector output. Active low. It responds directly to PFI input. If PFI

voltage is below the bandgap reference voltage, PFO is low. If PFI is above the

reference voltage, PFO output is high.

6

WDI

Digital Input

Watchdog timer input pin. This pin is typically used to monitor microprocessor

activity. It can assume three states: low, high and float. If WDI is floating or connected

to a high impedance three state buffer, the watchdog timer is not active, and the

corresponding watchdog output WDO is high. Watchdog timer is also not active any

time RESET_OD is low. Providing that RESET_OD is not asserted, any change of

state at WDI that is longer than 50ns will start the timer, or restart it, if the timer is

already running (Figure 3.). If there is no activity within the timeout period, nominally

1.6sec, the timer will stop running and WDO output will go low (Figure 3).

7

RESET_OD

Open Drain

Digital Output

Reset output. Active low open drain output. This pin is pulled up with a resistor

consistant with the sink and voltage current as specified in the electrical characteristics

input MR.

up to the reset threshold, nominally 4.65V. Once this threshold is reached, an internal

RESET_OD timer is activated. During the countdown RESET_OD output is kept low.

It is raised high upon completion of countdown, typically after 200ms. If a brown out

condition occurs during the reset timer countdown, the reset timer would be reset and

If MR is asserted low, RESET_OD is forced low and the reset timer is kept reset.

When MR is released high, the timer is activated and RESET_OD is kept low until

completion of the reset timeout, when it is raised high.