S3C4530A datasheet(13/432 Pages) SAMSUNG

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S3C4530A

PRODUCT OVERVIEW

1-13

Table 1-1. S3C4530A Signal Descriptions (Continued)

Signal

Pin No.

Type

Description

P[1:0]

179, 176

I/O

General I/O ports. See the I/O ports, chapter 12.

XINTREQ[3:0]

P[11:8]

191 - 189,

186

I/O

External interrupt request lines or general I/O ports.

See the I/O ports, chapter 12.

nXDREQ[1:0]/

P[13:12]

193, 192

I/O

Not External DMA requests for GDMA or general I/O ports.

See the I/O ports, chapter 12.

nXDACK[1:0]

P[15:14]

195, 194

I/O

Not External DMA acknowledge from GDMA or general I/O ports.

See the I/O ports, chapter 12.

TOUT0/P[16]

196

I/O

Timer 0 out or general I/O port. See the I/O ports, chapter 12.

TOUT1/P[17]

199

I/O

Timer 1 out or general I/O port. See the I/O ports, chapter 12.

SCL

200

I/O

I2C serial clock.

SDA

201

I/O

I2C serial data.

VDDP

1, 21, 41,

56, 78, 92,

105, 118,

130, 155,

167, 177,

197

Power

I/O pad power

VDDI

11, 31, 51,

65, 103,

142, 157,

187, 207

Power

Internal core power

VSSP

2, 22, 42,

57, 79, 81,

93, 106,

119, 131,

156, 168,

178, 198

GND

I/O pad ground

VSSI

12, 32, 52,

66, 104,

143, 158,

188, 208

GND

Internal core ground

VDDA

Power

Analog power for PLL

VSSA/VBBA

GND

Analog/Bulk ground for PLL

NOTE: SDRAM or EDO/normal DRAM interface signal pins are shared functions. It

′s functions will be configured by

SYSCFG[31].

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