AX88796L datasheet(37/71 Pages) ASIX

37 / 71 page

ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

5.1.9 Inter-frame gap (IFG) Offset 16H (Read/Write)

FIELD

NAME

DESCRIPTION

Reserved

6:0

IFG

Inter-frame Gap. Default value 15H.

5.1.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)

FIELD

NAME

DESCRIPTION

Reserved

6:0

IFG

Inter-frame Gap Segment 1. Default value 0cH.

5.1.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)

FIELD

NAME

DESCRIPTION

Reserved

6:0

IFG

Inter-frame Gap Segment 2. Default value 12H.

5.1.12 MII/EEPROM Management Register (MEMR) Offset 14H

(Read/Write)

FIELD

NAME

DESCRIPTION

EECLK EECLK:

EEPROM Clock

EEO

EEO : (Read only)

EEPROM Data Out value. That reflects Pin-48 EEDO value.

EEI

EEPROM Data In. That output to Pin-49 EEDI as EEPROM data input value.

EECS

EEPROM Chip Select

MDO

MII Data Out. The value reflects to Pin-66 MDIO when MDIR=0.

MDI

MDI: (Read only)

MII Data In. That reflects Pin-66 MDIO value.

MDIR

MII STA MDIO signal Direction

MII Read Control Bit, asserts this bit let MDIO signal as the input signal. Deassert this bit

let MDIO as output signal.

MDC

MII Clock. This value reflects to Pin-67 MDC.

5.1.13 Test Register (TR) Offset 15H (Write)

FIELD

NAME

DESCRIPTION

7:5

Reserved

TF16T

Test for Collision, default value is logic 0 (User always keep the default value unchanged)

TPE

Test pin Enable, default value is logic 0 (User always keep the default value unchanged)

2:0

IFG

Select Test Pins Output, default value is logic 0 (User always keep the default value

unchanged)

AX88796L Datasheet(PDF) 37 Page - ASIX Electronics Corporation

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