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LM3554TMX/NOPB Datasheet(PDF) 27 Page - Texas Instruments |
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LM3554TMX/NOPB Datasheet(HTML) 27 Page - Texas Instruments |
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27 / 47 page ![]() Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Not Used Bit 7 Bit 6 MSB LSB GPIO Register Register Address 0x20 NTC External Flag Data Data Direction Data Data Direction TX1/TORCH/ GPIO1 ENVM/ TX2/GPIO2 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 N/A Bit 7 Bit 6 MSB LSB Configuration Register 2 Register Address 0xF0 N/A AET Mode NTC Shutdown TX2 Shutdown VIN Monitor Mode N/A N/A 27 LM3554 www.ti.com SNVS549C – JUNE 2009 – REVISED FEBRUARY 2016 Product Folder Links: LM3554 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated 7.6.1.6 Configuration Register 2 Configuration Register 2 contains the bits to select if TX2, NTC, and the VIN monitor force torch mode or force the flash LEDs into shutdown. Additionally, bit [2] (AET bit) selects the AET mode (see and Table 7). Configuration Register 2 Description Table 7. Configuration Register 2 Bit Settings Bit 7 (Not used) Bit 6 (Not used) Bit 5 (Not used) Bit 4 (Not used) Bit 3 (VIN Monitor Shutdown) Bit 2 (AET mode) Bit 1 (NTC Shutdown) Bit 0 (TX2 Shutdown) Reads Back 1 Reads Back 1 Reads Back 1 Reads Back 1 0 = If IN drops below the programmed threshold and the VIN Monitor feature is enabled, the LED's are forced into Torch mode (default) 0 = Normal operation for TX1/TORCH high before STROBE (TX1 mode only) default 0 = LEDI/NTC pin going below VTRIP forces the LEDs into Torch mode (NTC mode only) default 0 = TX2 event forces the LEDs into Torch mode (TX2 mode only) default 1 = If IN drops below the programmed threshold and the VIN Monitor feature is enabled, the LED's turn off 1 = Alternative External Torch operation. TX1/TORCH high before STROBE forces Torch mode with no timeout (TX1 mode only) 1 = LEDI/NTC pin going below VTRIP forces the LEDs into shutdown (NTC mode only) 1 = TX2 event forces the LEDs into shutdown (TX2 mode only) 7.6.1.7 GPIO Register The GPIO register contains the control bits which change the state of the TX1/TORCH/GPIO1 pin and the ENVM/TX2/GPIO2 pin to general purpose I/O’s (GPIO’s). Additionally, bit[6] of this register configures the ENVM/TX2/GPIO2 as a hardware interrupt output reflecting the NTC flag bit in the Flags Register. and Table 8 describe the bit description and functionality of the GPIO register. GPIO Register Description |
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