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AD8284WCSVZ Datasheet(PDF) 19 Page - Analog Devices

Part # AD8284WCSVZ
Description  Radar Receive Path AFE - 4-Channel Mux
PDF  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD8284WCSVZ Datasheet(HTML) 19 Page - Analog Devices

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Data Sheet
AD8284
Rev. D | Page 19 of 28
Figure 22. Serial Timing Details
Table 9. Serial Timing Definitions
Parameter
Minimum Timing (ns)
Description
tDS
5
Setup time between the data and the rising edge of SCLK.
tDH
2
Hold time between the data and the rising edge of SCLK.
tCLK
40
Period of the clock.
tS
5
Setup time between CS and SCLK.
tH
2
Hold time between CS and SCLK.
tHI
16
Minimum period that SCLK should be in a logic high state.
tLO
16
Minimum period that SCLK should be in a logic low state.
tDIS_SDO
10
Minimum time it takes the SDO pin to switch between an output and a high impedance
node, relative to the rising edge of SCLK.
DON’T CARE
DON’T CARE
DON’T CARE
DON’T CARE
SDI
DON’T CARE
SDO
SCLK
CS
tS
tDH
tHI
tCLK
tLO
tDS
tH
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
D5
D4
D3
D2
D1
D0
OUTPUT DRIVER OFF
OUTPUT DRIVER ON
SCLK
tDIS_SDO



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