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S-7600A

Hardware Specification Revision 1.3

Seiko Instruments Inc.

5-4

5.2.2. x80 Family MPU Mode

This mode is selected by pulling the C86 input pin “L” and the PSX input pin “H”. In this mode, the

address and data are muxed onto a single 8-bit bus. All cycles start with the address placed on the bus.

This address is then latched internally on the rising edge of WRITEX. The RS pin “L” indicates that the

WRITEX strobe is for the address phase. In the next phase, data is either written or read by generating

WRITEX or READX strobe. The MPU interface logic will assert the BUSYX signal after READX or

WRITEX strobes are de-asserted. The BUSYX signal is de-asserted after the S-7600A complete a read

or writes operation. The MPU samples the BUSYX signal before starting a new cycle. The MPU can

initiate a new cycle after the BUSYX signal gets de-asserted.

5.2.2.1. Write Cycle Timing

Figure 5-3

x80 Family MPU Write Cycle Timing

Symbol

Description

Min

Max

Notes

TCYC8

System Cycle Time

100 ns

TAH8

Address Hold Time

20ns

TAW8

Address Setup Time

20ns

TDS8

Data Setup time

20ns

TDH8

Data Hold Time

20 ns

TCC8

Control Pulse Width

40 ns

1.9CLK

TBD8

BUSYX Delay Time

30ns

CL=80pF

TBC8

BUSYX Pulse Width

2CLK

TBOD8

BUSYX Output Disable Time

30ns

CL=80pF

NOTES:

• CLK is the clock of S-7600A

• Timing is specified of 50% of the signal waveform.

• Rise/fall time(20%,80%) of the input signal is 15nsec or less.

Table 5-5

x80 Family MPU Write Cycle Timing

READX

CLK

BUSYX

WRITEX

SD7 to 0

TAH8

TAW8

TCC8

TDH8

TDS8

TBD8

TBC8

TDH8

TAH8

TAW8

TCYC8

TCC8

TDS8

TBOD8

Address

read

Data

read

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