7

Rev:A Date: 11/20/03

SP6681 High Efficiency Boost Charge Pump Regulator

© Copyright 2002 Sipex Corporation

Figure 3. Typical SIM Card Application Circuit for the SP6681

Any standard CMOS logic output is suitable for

driving the C/4 or Cx8 control lines as long as

logic low is less than 0.4V and logic high is

greater than 1.3V.

Efficiency

Power efficiency with the SP6681 charge pump

regulator is improved over standard charge pumps

doubler circuits by the inclusion of an 1.5X

output mode, as described in the Theory of

Operation section. The net result is an increase

in efficiency at battery inputs greater than 3.7 to

3.8V where the SP6681 switches to the 1.5X

mode.

Figure 4. Capacitor Selection Test Circuit

n

i

p

K

L

Cn

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8

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P

M

U

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2

3

z

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k

8

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7

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1

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2

6

2

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8

6

7

.

2

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lz

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9

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2

Table 1. Control Line Logic for the Internal Charge

Pump Oscillator

V

OUT

C/4

Cx8

CLK

GND

SP6681

8

CF1P

CF1N

CF2P

CF2N

4.7µF

2.2µF

2

9

10

7

1

6

45

3

+3.6V

Lithium-Ion

Battery

V

IN

2.2µF

2.2µF

5.0V output

Power Supply

HP3631A

1000µF

0.25ohm

0.75” Leads

+

-

SP6681 EvBd

2.2µF Caps

Capacitor Selection

In order to maintain the lowest output resistance,

input ripple voltage and output ripple voltage,

multi-layer ceramic capacitors with inherently

low ESR are recommended. Refer to Table 2 for

some suggested low ESR capacitors. Tables of

output resistance and ripple voltages for a vari-

ety of input, output and pump capacitors are

included here to use as a guide in capacitor

selection. Measured conditions are with CLK =

32kHz, 5mA output load and all capacitors are

2.2uF except when stated otherwise.

A DC

power supply with added 0.25ohm output ESR

was used to simulate a Lithium Ion Battery as

shown in figure 4.

Board Layout

PC board layout is an important design consider-

ation to mitigate switching current effects. High

frequency operation makes PC layout important

for minimizing ground bounc and noise. Com-

ponents should be place as close to the IC as

possible with connections made through short,

low impedance traces.

To maximize output

ripple voltage, use a ground plane and solder the

IC's GND pin directly to the ground plane.