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PI6CDBL401B

Rev.C

03/23/16

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PI6CDBL401B

4-Output Low Power PCIE GEN1-2-3 Buffer

Pin Descriptions

Pin# Pin Name

Type

Description

1

HIBW_BYPM_

LOBW#

Input

Trilevel input to select High BW, Bypass or Low BW mode. See PLL Operating

Mode Table for Details.

2

FB_DNC

Output

True clock of differential feedback. The feedback output and feedback input are

connected internally on this pin. Do not connect anything to this pin.

3

FB_DNC#

Output

Complement clock of differential feedback. The feedback output and feedback

input are connected internally on this pin. Do not connect anything to this pin.

4

VDDR3.3

Power

3.3V power for differential input clock (receiver). This VDD should be treated as

an Analog power rail and filtered appropriately.

5

CLK_IN

Input

True Input for differential reference clock.

6

CLK_IN#

Input

Complementary Input for differential reference clock.

7

GNDR

Power

Analog Ground pin for the differential input (receiver)

8

GNDDIG

Power

Ground pin for digital circuitry

9

VDDDIG3.3

Power

3.3V digital power (dirty power)

10

SCLK_3.3

Input

Clock pin of SMBus circuitry, 3.3V tolerant.

11

SDATA_3.3

Input/Output Data pin for SMBus circuitry, 3.3V tolerant.

12

OE0#

Input

Active low input for enabling DIF pair 0. This pin has an internal pull-down. 1

=disable outputs, 0 = enable outputs

13

CLK0

Output

Differential true clock output

14

CLK0#

Output

Differential Complementary clock output

15

GND

Power

Ground pin.

16

VDDO1.8

Power

Power supply for outputs, range from 1.8V~3.3V.

17

OE1#

Input

Active low input for enabling DIF pair 1. This pin has an internal pull-down. 1

=disable outputs, 0 = enable outputs

18

CLK1

Output

Differential true clock output

19

CLK1#

Output

Differential Complementary clock output

20

GNDA

Power

Ground pin for the PLL core.

21

VDDA3.3

Power

3.3Vpower for the PLL core.

22

CLK2

Output

Differential true clock output

23

CLK2#

Output

Differential Complementary clock output

24

OE2#

Input

Active low input for enabling DIF pair 2. This pin has an internal pull-down. 1

=disable outputs, 0 = enable outputs

25

VDDO1.8

Power

Power supply for outputs, range from 1.8V~3.3V.

26

GND

Power

Ground pin.

27

CLK3

Output

Differential true clock output

28

CLK3#

Output

Differential Complementary clock output

29

OE3#

Input

Active low input for enabling DIF pair 3. This pin has an internal pull-down. 1

=disable outputs, 0 = enable outputs

30

GND

Power

Ground pin.

16-0064