IS25LP032 datasheet(13/90 Pages) ISSI

13 / 90 page

IS25LP032/064/128

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

10/03/2014

BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of

the memory area to be protected. Refer to Tables 6.3 for the Block Write Protection (BP) bit settings. When a

defined combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any

program or erase operation to that area will be inhibited.

Note: A Chip Erase (CER) instruction will be ignored unless

all the Block Protection Bits are “0”s.

SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection

(WP#) signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not

write-

protected. When the SRWD is set to “1” and the WP# is pulled low (VIL), the bits of Status Register

(SRWD, BP3, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is set to

“1” and WP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction.

QE bit: The Quad Enable (QE) is a non-volatile bit in the status register that allows quad operation. When the

QE bit is set to

“0”, the pin WP# and HOLD# are enabled. When the QE bit is set to “1”, the IO2 and IO3 pins

are enabled.

WARNING: The QE bit must be set to 0 if WP# or HOLD# pin is tied directly to the power supply or ground.

IS25LP032 Datasheet(PDF) 13 Page - Integrated Silicon Solution, Inc