PI7C8154A datasheet(13/114 Pages) PERICOM

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PI7C8154A

ASYNCHRONOUS 2-PORT

PCI-to-PCI BRIDGE

Advance Information

Page 13 of 112

DEC 2009 REVISION 1.02

Name

Pin #

Type

Description

P_IRDY#

AC5

STS

Primary IRDY (Active LOW). Driven by the

initiator of a transaction to indicate its ability to

complete current data phase on the primary side.

Once asserted in a data phase, it is not de-asserted

until the end of the data phase. Before tri-stated, it

is driven to a de-asserted state for one cycle.

P_TRDY#

AB5

STS

Primary TRDY (Active LOW). Driven by the

target of a transaction to indicate its ability to

complete current data phase on the primary side.

Once asserted in a data phase, it is not de-asserted

until the end of the data phase. Before tri-stated,

it is driven to a de-asserted state for one cycle.

P_DEVSEL#

AA6

STS

Primary Device Select (Active LOW). Asserted

by the target indicating that the device is accepting

the transaction. As a master, bridge waits for the

assertion of this signal within 5 cycles of

P_FRAME# assertion; otherwise, terminate with

master abort. Before tri-stated, it is driven to a

de-asserted state for one cycle.

P_STOP#

AC6

STS

Primary STOP (Active LOW). Asserted by the

target indicating that the target is requesting the

initiator to stop the current transaction. Before tri-

stated, it is driven to a de-asserted state for one

cycle.

P_LOCK#

AB6

Primary LOCK (Active LOW). Asserted by an

initiator, one clock cycle after the first address phase

of a transaction, attempting to perform an operation

that may take more than one PCI transaction to

complete.

P_IDSEL

Primary ID Select. Used as a chip select line for

Type 0 configuration access to bridge configuration

space.

P_PERR#

AC7

STS

Primary Parity Error (Active LOW). Asserted

when a data parity error is detected for data received

on the primary interface. Before being tri-stated, it

is driven to a de-asserted state for one cycle.

P_SERR#

Primary System Error (Active LOW). Can be

driven LOW by any device to indicate a system

error condition. Bridge drives this pin on:

Address parity error

Posted write data parity error on target bus

Secondary S_SERR# asserted

Master abort during posted write transaction

Target abort during posted write transaction

Posted write transaction discarded

Delayed write request discarded

Delayed read request discarded

Delayed transaction master timeout

This signal requires an external pull-up resistor for

proper operation.

P_REQ#

Primary Request (Active LOW): This is asserted

by BRIDGE to indicate that it wants to start a

transaction on the primary bus. Bridge de-asserts

this pin for at least 2 PCI clock cycles before

asserting it again.

P_GNT#

Primary Grant (Active LOW): When asserted,

PI7C8154A can access the primary bus. During idle

and P_GNT# asserted, bridge will drive P_AD,

P_CBE, and P_PAR to valid logic levels.

P_RESET#

Primary RESET (Active LOW): When

P_RESET# is active, all PCI signals should be

asynchronously tri-stated.

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