ADC1251CMJSLASH883 datasheet(5/16 Pages) NSC

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Electrical Characteristics (Continued)

Note 6

Two on-chip diodes are tied to the analog input as shown below Errors in the AD conversion can occur if these diodes are forward biased more than

50 mV This means that if AVCC and DVCC are minimum (475 VDC) and V

is maximum (b475 VDC) the analog input full-scale voltage must be s g48 VDC

TLH11024 – 4

Note 7

A diode exists between AVCC and DVCC as shown below

TLH11024 – 5

To guarantee accuracy it is required that the AVCC and DVCC be connected together to a power supply with separate bypass filters at each VCC pin

Note

Accuracy is guaranteed at fCLK e 35 MHz At higher or lower clock frequencies accuracy may degrade See the Typical Performance Characteristics

curves

Note

Typicals are at TJ e 25 C and represent most likely parametric norm

Note 10

Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)

Note 11

Positive linearity error is defined as the deviation of the analog value expressed in LSBs from the straight line that passes through positive full scale and

zero For negative linearity error the straight line passes through negative full scale and zero (See

Figures 1b and 1c )

Note 12

The ADC1251’s self-calibration technique ensures linearity full scale and offset errors as specified but noise inherent in the self-calibration process will

result in a repeatability uncertainty of g020 LSB

Note 13

If TA changes then an Auto-Zero or Auto-Cal cycle will have to be re-started See the typical performance characteristic curves

Note 14

After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes

Note 15

When using the WR control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the

end of the interval tA therefore making tA end a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR If the falling edge of the clock

is synchronous to the rising edge of WR then tA will end exactly 65 clock periods after the rising edge of WR This does not occur when S H control is used

Note 16

The CAL line must be high before a conversion is started

Note 17

The specifications for these parameters are valid after an Auto-Cal cycle has been completed

Note 18

The ADC1251 reference ladder is composed solely of capacitors

Note 19

A Military RETS Electrical Test Specification is available on request At time of printing the ADC1251CMJ883 RETS specification complies fully with the

boldface

limits in this column

TLH11024 – 6

FIGURE 1a Transfer Characteristic

ADC1251CMJ/883 Datasheet(PDF) 5 Page - National Semiconductor (TI)

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