MB9AAA0N datasheet(5/109 Pages) SPANSION

5 / 109 page

D a t a S h e e t

MB9AAA0N_DS706-00067-2v0-E, June 30, 2015

CONFIDENTIAL

 Features

 32-bit ARM Cortex-M3 Core

 Processor version: r2p1

 Up to 20MHz Operation Frequency

 Integrated Nested Vectored Interrupt Controller (NVIC): 1 channel NMI (non-maskable interrupt) and

32 channels' peripheral interrupts and 8 priority levels

 24-bit System timer (Sys Tick): System timer for OS task management

 On-chip Memories

[Flash memory]

 Up to 128 Kbytes

 Read cycle: 0 wait-cycle

 Security function for code protection

[SRAM]

This series contains a total of up to 16 Kbyte on-chip SRAM that is connected to System bus of Cortex-M3

core.

 SRAM1: Up to 16 Kbytes

 LCD controller (LCDC)

 Selectable from 44 SEG × 4 COM (Max) or 40 SEG × 8 COM (Max)

 Internal divide resistor is contained (selectable from 10 kΩ or 100 kΩ for the resistor value)

 LCD drive power supply (bias) pin (VV4 to VV0)

 Interrupt function synchronized with the LCD module frame frequency

 With blinking function

 Inverted display function

 Multi-function Serial Interface (Max 8 channels)

Operation mode is selectable from the followings for each channel.

 UART

 CSIO

 I2C

[UART]

 Full duplex double buffer

 Selection with or without parity supported

 Built-in dedicated baud rate generator

 External clock available as a serial clock

 Various error detection functions available (parity errors, framing errors, and overrun errors)

[CSIO]

 Full duplex double buffer

 Built-in dedicated baud rate generator

 Overrun error detection function available

2C]

Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported

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