about output timing, a simple way to capture a valid output is

to latch the data on the falling edge of the conversion clock

(pin 10).

Be very careful when driving a high capacitance bus. The

more capacitance the output drivers must charge for each

conversion, the more instantaneous digital current flows

through V

spikes can cause on-chip ground noise and couple into the

analog circuitry, degrading dynamic performance. Adequate

bypassing and careful attention to the ground plane will

reduce this problem. Additionally, bus capacitance beyond

the specified 20 pF/pin will cause t

difficult to properly latch the ADC output data. The result

could be an apparent reduction in dynamic performance.

To minimize noise due to output switching, minimize the load

currents at the digital outputs. This can be done by connect-

ing buffers between the ADC outputs and any other circuitry

(74ACQ541, for example). Only one input should be con-

nected to each output pin. Additionally, inserting series re-

sistors of 47

Ω to 56Ω at the digital outputs, close to the ADC

pins, will isolate the outputs from trace and other circuit

capacitances and limit the output currents, which could oth-

erwise result in performance degradation. See Figure 4.

20046013

FIGURE 4. Application Circuit using Transformer or Differential OpAmp Drive Circuit

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