MB9B320TA datasheet(91/141 Pages) SPANSION

91 / 141 page

D a t a S h e e t

MB9B320TA_DS706-00062-2v0-E, January 30, 2015

CONFIDENTIAL

(4-1) Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL)

(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)

Parameter

Symbol

Value

Unit

Remarks

Min

Typ

Max

PLL oscillation stabilization wait time*

(LOCK UP time)

tLOCK

100

μs

PLL input clock frequency

FPLLI

MHz

PLL multiplication rate

multiplier

PLL macro oscillation clock frequency

FPLLO

150

MHz

Main PLL clock frequency*

FCLKPLL

MHz

USB clock frequency*

FCLKSPLL

MHz

After the M frequency

division

*1 : Time from when the PLL starts operating until the oscillation stabilizes.

*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family

PERIPHERAL MANUAL".

*3 : For more information about USB clock, see "CHAPTER 2-2: USB Clock Generation" in "FM3 Family

PERIPHERAL MANUAL Communication Macro Part".

(4-2) Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock

of main PLL)

(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 105°C)

Parameter

Symbol

Value

Unit

Remarks

Min

Typ

Max

PLL oscillation stabilization wait time*

(LOCK UP time)

tLOCK

100

μs

PLL input clock frequency

FPLLI

3.8

4.2

MHz

PLL multiplication rate

multiplier

PLL macro oscillation clock frequency

FPLLO

150

MHz

Main PLL clock frequency*

FCLKPLL

MHz

*1 : Time from when the PLL starts operating until the oscillation stabilizes.

*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family

PERIPHERAL MANUAL".

Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the

frequency/temperature has been trimmed.

Main clock (CLKMO)

divider

PLL input

clock

USB PLL

divider

USB

clock

divider

USB PLL connection

PLL macro

oscillation clock

divider

PLL input

clock

Main

PLL

PLL macro

oscillation clock

divider

Main PLL

clock

(CLKPLL)

divider

Main PLL connection

High-speed CR clock (CLKHC)

Main clock (CLKMO)

MB9B320TA Datasheet(PDF) 91 Page - SPANSION

MB9B320TA Datasheet(HTML) 91 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL