TABLE 4. ADC12L032 and ADC12L030 Multiplexer Addressing

Analog Channel Addressed

A/D Input

Multiplexer

Mode

MUX

and Assignment

Polarity

Output

Address

with A/DIN1 tied to MUXOUT1

Assignment

Channel

and A/DIN2 tied to MUXOUT2

Assignment

DI0

DI1

CH0

CH1

COM

A/DIN1

A/DIN2

MUXOUT1

MUXOUT2

L

L

+

−

+

−

CH0

CH1

Differential

L

H

−

+

−

+

CH0

CH1

H

L

+

−

+

−

CH0

COM

Single-Ended

H

H

+

−

+

−

CH1

COM

Note 21: ADC12L030 does not have A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 pins.

TABLE 5. Mode Programming

ADC12L038

DI0

DI1

DI2

DI3

DI4

DI5

DI6

DI7

Mode Selected

(Current)

DO Format

(next Conversion

Cycle)

ADC12L034

DI0

DI1

DI2

DI3

DI4

DI5

DI6

ADC12L030

and

DI0

DI1

DI2

DI3

DI4

DI5

ADC12L032

See

Tables 2, 3, 4

LLLL

12 Bit Conversion

12 or 13 Bit MSB First

See

Tables 2, 3, 4

L

L

L

H

12 Bit Conversion

16 or 17 Bit MSB First

See

Tables 2, 3, 4

L

L

H

L

8 Bit Conversion

8 or 9 Bit MSB First

L

L

L

L

L

L

H

H

12 Bit Conversion of Full-Scale

12 or 13 Bit MSB First

See

Tables 2, 3, 4

L

H

L

L

12 Bit Conversion

12 or 13 Bit LSB First

See

Tables 2, 3, 4

L

H

L

H

12 Bit Conversion

16 or 17 Bit LSB First

See

Tables 2, 3, 4

L

H

H

L

8 Bit Conversion

8 or 9 Bit LSB First

L

L

L

L

L

H

H

H

12 Bit Conversion of Offset

12 or 13 Bit LSB First

L

L

L

L

H

L

L

L

Auto Cal

No Change

L

L

L

L

H

L

L

H

Auto Zero

No Change

L

L

L

L

H

L

H

L

Power Up

No Change

L

L

L

L

H

L

H

H

Power Down

No Change

L

L

L

L

H

H

L

L

Read Status Register

No Change

L

L

L

L

H

H

L

H

Data Out without Sign

No Change

H

L

L

L

H

H

L

H

Data Out with Sign

No Change

L

L

L

L

H

H

H

L

Acquisition Time — 6 CCLK

Cycles

No Change

L

H

L

L

H

H

H

L

Acquisition Time — 10 CCLK

Cycles

No Change

H

L

L

L

H

H

H

L

Acquisition Time — 18 CCLK

Cycles

No Change

H

H

L

L

H

H

H

L

Acquisition Time — 34 CCLK

Cycles

No Change

L

L

L

L

HHHH

User Mode

No Change

H

X

X

X

HHHH

Test Mode

No Change

(CH1–CH7 become Active

Outputs)

X = Don’t Care

Note 22: The A/D powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB first and user mode.

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