Data Sheet

HMC6545

Rev. A | Page 13 of 23

Protocol

Table 11 lists the definitions and conditions occurring in a

2-wire data transfer.

Figure 28 shows a representation of a complete communication

cycle on the 2-wire interface.

The master generates a start condition to indicate the beginning

of a new data transfer.

The master then starts generating clock pulses on SCL and

transmits the first byte on SDA. This first byte always consists of

a 7-bit slave address followed by one bit that indicates the read/

write direction (R/W). The device on the bus with a matching

address generates an acknowledge.

The master continues generating more clock pulses on SCL and,

depending on the value of the R/W bit, sends (write operation,

R/W = 0) or receives (read operation, R/W = 1) data on SDA.

In each case, the receiver must acknowledge the data sent by the

transmitter. This sequence of 8-bit data followed by a 1-bit

acknowledge can be repeated multiple times.

When all data communication is over for the current transfer

cycle, the master indicates the end of data transfer by generating

a stop condition.

Data Transfer Formats

Write Cycle

In a write cycle, the master transmitter sends data to the slave

receiver. The transfer direction is from master to slave and does

not change (see Figure 29). The master generates a start condition

followed by a 7-bit slave address and by the R/W bit set to 0.

The slave with a matching address replies with an acknowledge.

The master then transmits the first byte to the slave device. This

first byte is an address of the internal registers of the slave. The

slave device replies with an acknowledge bit. For a subsequent

read cycle, the master generates a stop bit; otherwise, the master

then transmits the next byte, which is a data byte to be stored in

the internal slave register previously addressed. This data byte is

followed by an acknowledge bit from the slave. This process can

continue for multiple bytes, and the slave device increments its

internal register address count as it receives subsequent bytes

from the master. When all data transfer is over, the master

generates a stop condition to end the cycle.

Table 11. 2-Wire Data Transfer Terminology and Definitions

Term

Definition

Start

A start condition is always generated by the master and is defined as a high to low transition on the SDA line while SCL is

high. The bus becomes busy after a start condition.

Stop

A stop condition is always generated by the master and is defined as a low to high transition on the SDA line while SCL is

high. The bus becomes free after the stop condition occurs.

Byte Format

Every byte transmitted on SDA must be eight bits long and is transferred with the most significant bit (MSB) first. Each

byte must be followed by an acknowledge bit.

Data Valid

Condition

For data to be considered valid, the SDA line must be stable during the entire high period of its respective clock pulse.

Acknowledge

For each byte sent or received on the bus, the master generates an extra clock cycle that is used for acknowledgement,

for a total of nine bits. The transmitter releases the SDA line, which is pulled high by the external resistor, and the receiver

must pull down the SDA line and drive it low while SCL is high during this entire clock cycle to indicate acknowledgment.

SDA is left high during this clock cycle to indicate a no acknowledge (NACK) situation, usually because the device

addressed is unable to receive or transmit the data requested.

Figure 28. Complete Data Transfer

Figure 29. Write Cycle

1

2

7

8

9

7

8

9

1

2

7

8

9

1

2

SDA

SCL

START

CONDITION

STOP

CONDITION

MSB

ADDRESS

DATA

ACK

ACK

DATA

ACK

R/W

START

R/W = 0

ACK

ACK

STOP

NACK

DATA BYTE

ACK

ADDRESS BYTE

DATA BYTE

SLAVE ADDRESS

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER