ADuM3151ARSZ datasheet(19/22 Pages) AD

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Data Sheet

ADuM3151/ADuM3152/ADuM3153

synchronized or pushed apart when they are presented at the

output. Edge order is always preserved for as long as the edges

are separated by at least VIx SKEW. In other words, if one edge is

leading another at the input, the order of the edges is not

reversed by the isolator.

PRINTED CIRCUIT BOARD (PCB) LAYOUT

The ADuM3151/ADuM3152/ADuM3153 digital isolators

require no external interface circuitry for the logic interfaces.

Power supply bypassing is strongly recommended at both input

and output supply pins: VDD1 and VDD2 (see Figure 15). The

capacitor value must be between 0.01 µF and 0.1 µF. The total

lead length between both ends of the capacitor and the input

power supply pin must not exceed 20 mm.

BYPASS < 2mm

VDD1

GND1

MCLK

MSS

VIA/VOA

VIB/VOB

VDD2

GND2

SCLK

SSS

VOA/VIB

VIB/VOB

VOC

GND1

VIC

GND2

ADuM3151/

ADuM3152/

ADuM3153

Figure 15. Recommended PCB Layout

In applications involving high common-mode transients, it is

important to minimize board coupling across the isolation

barrier. Furthermore, design the board layout so that any

coupling that does occur affects all pins equally on a given

component side. Failure to ensure this can cause voltage

differentials between pins exceeding the absolute maximum

ratings of the device, thereby leading to latch-up or permanent

damage.

PROPAGATION DELAY RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes

a logic signal to propagate through a component. The input to

output propagation delay time for a high to low transition may

differ from the propagation delay time of a low to high

transition.

INPUT

OUTPUT

tPLH

tPHL

50%

Figure 16. Propagation Delay Parameters

Pulse width distortion is the maximum difference between

these two propagation delay values and an indication of how

accurately the timing of the input signal is preserved.

Channel to channel matching refers to the maximum amount

the propagation delay differs between channels within a single

ADuM3151/ADuM3152/ADuM3153 component.

DC CORRECTNESS AND MAGNETIC FIELD

IMMUNITY

Positive and negative logic transitions at the isolator input cause

narrow (~1 ns) pulses to be sent via the transformer to the decoder.

The decoder is bistable and is, therefore, either set or reset by

the pulses indicating input logic transitions. In the absence of

logic transitions at the input for more than ~1.2 µs, a periodic

set of refresh pulses indicative of the correct input state are sent

via the low speed channel to ensure dc correctness at the output.

If the low speed decoder receives no pulses for more than about

5 µs, the input side is assumed to be unpowered or nonfunctional,

in which case, the isolator output is forced to a high-Z state by

the watchdog timer circuit.

The limitation on the magnetic field immunity of the device is

set by the condition in which induced voltage in the transformer

receiving coil is sufficiently large to either falsely set or reset the

decoder. The following analysis defines such conditions. The

ADuM3151/ADuM3152/ADuM3153 were examined in a 3 V

operating condition because it represents the most susceptible

mode of operation for this product.

The pulses at the transformer output have an amplitude greater

than 1.5 V. The decoder has a sensing threshold of about 1.0 V;

thereby, establishing a 0.5 V margin in which induced voltages

can be tolerated. The voltage induced across the receiving coil is

given by

V = (−dβ/dt)∑πrn2; n = 1, 2, …, N

where:

β is the magnetic flux density.

rn is the radius of the nth turn in the receiving coil.

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM3151/

ADuM3152/ADuM3153 and an imposed requirement that the

induced voltage be, at most, 50% of the 0.5 V margin at the

decoder, a maximum allowable magnetic field is calculated as

shown in Figure 17.

MAGNETIC FIELD FREQUENCY (Hz)

0.001

100

100M

0.1

0.01

10k

100k

10M

Figure 17. Maximum Allowable External Magnetic Flux Density

Rev. A | Page 19 of 22

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