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CLC030VEC Datasheet(PDF) 17 Page - National Semiconductor (TI) |
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CLC030VEC Datasheet(HTML) 17 Page - National Semiconductor (TI) |
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17 / 29 page  Device Operation (Continued) TABLE 2. Control Register Bit Assignments (Continued) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TEST 0 (register address 0Dh) PASS/FAIL TPG ENABLE TEST PATTERN SELECT(5) TEST PATTERN SELECT(4) TEST PATTERN SELECT(3) TEST PATTERN SELECT(2) TEST PATTERN SELECT(1) TEST PATTERN SELECT(0) VIDEO INFO 0 (register address 0Eh) DITHER ENABLE VERT. DITHER ENABLE VPG FILTER ENABLE LOCK DETECT EAV SAV NSP reserved MULTI-FUNCTION I/O BUS PIN CONFIGURATION I/O PIN 0 CONFIG (register address 0Fh) reserved reserved PIN 0 SEL[5] PIN 0 SEL[4] PIN 0 SEL[3] PIN 0 SEL[2] PIN 0 SEL[1] PIN 0 SEL[0] I/O PIN 1 CONFIG (register address 10h) reserved reserved PIN 1 SEL[5] PIN 1 SEL[4] PIN 1 SEL[3] PIN 1 SEL[2] PIN 1 SEL[1] PIN 1 SEL[0] I/O PIN 2 CONFIG (register address 11h) reserved reserved PIN 2 SEL[5] PIN 2 SEL[4] PIN 2 SEL[3] PIN 2 SEL[2] PIN 2 SEL[1] PIN 2 SEL[0] I/O PIN 3 CONFIG (register address 12h) reserved reserved PIN 3 SEL[5] PIN 3 SEL[4] PIN 3 SEL[3] PIN 3 SEL[2] PIN 3 SEL[1] PIN 3 SEL[0] I/O PIN 4 CONFIG (register address 13h) reserved reserved PIN 4 SEL[5] PIN 4 SEL[4] PIN 4 SEL[3] PIN 4 SEL[2] PIN 4 SEL[1] PIN 4 SEL[0] I/P PIN 5 CONFIG (register address 14h) reserved reserved PIN 5 SEL[5] PIN 5 SEL[4] PIN 5 SEL[3] PIN 5 SEL[2] PIN 5 SEL[1] PIN 5 SEL[0] I/O PIN 6 CONFIG (register address 15h) reserved reserved PIN 6 SEL[5] PIN 6 SEL[4] PIN 6 SEL[3] PIN 6 SEL[2] PIN 6 SEL[1] PIN 6 SEL[0] I/O PIN 7 CONFIG (register address 16h) reserved reserved PIN 7 SEL[5] PIN 7 SEL[4] PIN 7 SEL[3] PIN 7 SEL[2] PIN 7 SEL[1] PIN 7 SEL[0] TEST MODE 0 (register address 55h) reserved reserved SYNC DETECT ENABLE LSB CLIPPING reserved NRZI ENABLE SCRAMBLER ENABLE reserved www.national.com 17 |
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