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PIC16F876ATI/ML Datasheet(PDF) 152 Page - Microchip Technology |
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PIC16F876ATI/ML Datasheet(HTML) 152 Page - Microchip Technology |
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152 / 234 page  PIC16F87XA DS39582B-page 150 2003 Microchip Technology Inc. TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset Wake-up via WDT or Interrupt W 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu INDF 73A 74A 76A 77A N/A N/A N/A TMR0 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu PCL 73A 74A 76A 77A 0000 0000 0000 0000 PC + 1(2) STATUS 73A 74A 76A 77A 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu PORTA 73A 74A 76A 77A --0x 0000 --0u 0000 --uu uuuu PORTB 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu PORTC 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu PORTD 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu PORTE 73A 74A 76A 77A ---- -xxx ---- -uuu ---- -uuu PCLATH 73A 74A 76A 77A ---0 0000 ---0 0000 ---u uuuu INTCON 73A 74A 76A 77A 0000 000x 0000 000u uuuu uuuu(1) PIR1 73A 74A 76A 77A r000 0000 r000 0000 ruuu uuuu(1) 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu(1) PIR2 73A 74A 76A 77A -0-0 0--0 -0-0 0--0 -u-u u--u(1) TMR1L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu T1CON 73A 74A 76A 77A --00 0000 --uu uuuu --uu uuuu TMR2 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu T2CON 73A 74A 76A 77A -000 0000 -000 0000 -uuu uuuu SSPBUF 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu CCPR1L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 73A 74A 76A 77A --00 0000 --00 0000 --uu uuuu RCSTA 73A 74A 76A 77A 0000 000x 0000 000x uuuu uuuu TXREG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu RCREG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu CCPR2L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu CCPR2H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu ADRESH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 73A 74A 76A 77A 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu TRISA 73A 74A 76A 77A --11 1111 --11 1111 --uu uuuu TRISB 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu TRISC 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition, r = reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-5 for Reset value for specific condition. |
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