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PIC16F876ATI/ML Datasheet(PDF) 229 Page - Microchip Technology |
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PIC16F876ATI/ML Datasheet(HTML) 229 Page - Microchip Technology |
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229 / 234 page  2003 Microchip Technology Inc. DS39582B-page 227 PIC16F87XA I2C Bus Data ............................................................ 191 I2C Bus Start/Stop Bits ............................................. 190 I2C Master Mode (Reception, 7-bit Address) ........... 103 I2C Master Mode (Transmission, 7 or 10-bit Address) ......................................... 102 I2C Slave Mode (Transmission, 10-bit Address) ........ 89 I2C Slave Mode (Transmission, 7-bit Address) .......... 87 I2C Slave Mode with SEN = 1 (Reception, 10-bit Address) ................................................... 93 I2C Slave Mode with SEN = 0 (Reception, 10-bit Address) ................................................... 88 I2C Slave Mode with SEN = 0 (Reception, 7-bit Address) ..................................................... 86 I2C Slave Mode with SEN = 1 (Reception, 7-bit Address) ..................................................... 92 Parallel Slave Port (PIC16F874A/877A Only) .......... 187 Parallel Slave Port (PSP) Read ................................. 52 Parallel Slave Port (PSP) Write ................................. 52 Repeat Start Condition ............................................. 100 Reset, Watchdog Timer, Start-up Timer and Power-up Timer ........................................ 184 Slave Mode General Call Address Sequence (7 or 10-bit Address Mode) ................................ 94 Slave Synchronization ............................................... 77 Slow Rise Time (MCLR Tied to VDD via RC Network) .................................................... 152 SPI Master Mode (CKE = 0, SMP = 0) .................... 188 SPI Master Mode (CKE = 1, SMP = 1) .................... 188 SPI Mode (Master Mode) ........................................... 76 SPI Mode (Slave Mode with CKE = 0) ....................... 78 SPI Mode (Slave Mode with CKE = 1) ....................... 78 SPI Slave Mode (CKE = 0) ...................................... 189 SPI Slave Mode (CKE = 1) ...................................... 189 Stop Condition Receive or Transmit Mode .............. 104 Synchronous Reception (Master Mode, SREN) ...................................... 124 Synchronous Transmission ...................................... 122 Synchronous Transmission (Through TXEN) .......... 122 Time-out Sequence on Power-up (MCLR Not Tied to VDD) Case 1 .............................................................. 152 Case 2 .............................................................. 152 Time-out Sequence on Power-up (MCLR Tied to VDD via RC Network) ................................... 151 Timer0 and Timer1 External Clock .......................... 185 USART Synchronous Receive (Master/Slave) .................................................. 193 USART Synchronous Transmission (Master/Slave) .................................................. 193 Wake-up from Sleep via Interrupt ............................ 157 Timing Parameter Symbology .......................................... 181 TMR0 Register ................................................................... 19 TMR1CS Bit ....................................................................... 57 TMR1H Register ................................................................ 19 TMR1L Register ................................................................. 19 TMR1ON Bit ....................................................................... 57 TMR2 Register ................................................................... 19 TMR2ON Bit ....................................................................... 61 TMRO Register .................................................................. 21 TOUTPS0 Bit ..................................................................... 61 TOUTPS1 Bit ..................................................................... 61 TOUTPS2 Bit ..................................................................... 61 TOUTPS3 Bit ..................................................................... 61 TRISA Register .................................................................. 20 TRISB Register .................................................................. 20 TRISC Register .................................................................. 20 TRISD Register .................................................................. 20 TRISE Register .................................................................. 20 IBF Bit ........................................................................ 50 IBOV Bit ..................................................................... 50 OBF Bit ...................................................................... 50 PSPMODE Bit ........................................... 48, 49, 50, 51 TXREG Register ................................................................ 19 TXSTA Register ................................................................. 20 BRGH Bit ................................................................. 111 CSRC Bit ................................................................. 111 SYNC Bit ................................................................. 111 TRMT Bit .................................................................. 111 TX9 Bit ..................................................................... 111 TX9D Bit .................................................................. 111 TXEN Bit .................................................................. 111 U USART ............................................................................. 111 Address Detect Enable (ADDEN Bit) ....................... 112 Asynchronous Mode ................................................ 115 Asynchronous Receive (9-bit Mode) ........................ 119 Asynchronous Receive with Address Detect. See Asynchronous Receive (9-bit Mode). Asynchronous Receiver ........................................... 117 Asynchronous Reception ......................................... 118 Asynchronous Transmitter ....................................... 115 Baud Rate Generator (BRG) ................................... 113 Baud Rate Formula ......................................... 113 Baud Rates, Asynchronous Mode (BRGH = 0) .............................................. 114 Baud Rates, Asynchronous Mode (BRGH = 1) .............................................. 114 High Baud Rate Select (BRGH Bit) ................. 111 Sampling .......................................................... 113 Clock Source Select (CSRC Bit) .............................. 111 Continuous Receive Enable (CREN Bit) .................. 112 Framing Error (FERR Bit) ........................................ 112 Mode Select (SYNC Bit) .......................................... 111 Overrun Error (OERR Bit) ........................................ 112 Receive Data, 9th Bit (RX9D Bit) ............................. 112 Receive Enable, 9-bit (RX9 Bit) ............................... 112 Serial Port Enable (SPEN Bit) ..........................111, 112 Single Receive Enable (SREN Bit) .......................... 112 Synchronous Master Mode ...................................... 121 Synchronous Master Reception ............................... 123 Synchronous Master Transmission ......................... 121 Synchronous Slave Mode ........................................ 124 Synchronous Slave Reception ................................. 125 Synchronous Slave Transmit ................................... 124 Transmit Data, 9th Bit (TX9D) ................................. 111 Transmit Enable (TXEN Bit) .................................... 111 Transmit Enable, 9-bit (TX9 Bit) .............................. 111 Transmit Shift Register Status (TRMT Bit) .............. 111 USART Synchronous Receive Requirements ................. 193 V VDD Pin ...........................................................................9, 13 Voltage Reference Specifications .................................... 180 VSS Pin ...........................................................................9, 13 |
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