FM24V02A datasheet(13/19 Pages) CYPRESS

13 / 19 page

FM24V02A

Document Number: 001-90839 Rev. *G

Page 13 of 19

AC Switching Characteristics

Over the Operating Range

Parameter[7]

Alt.

Parameter

Description

Fast-Mode Plus (Fm+) [9]

Hs-Mode[9]

Unit

Min

Max

Min

Max

fSCL[8]

SCL clock frequency

–

1.0

–

3.4

MHz

tSU; STA

Start condition setup for repeated Start

260

–

160

–

tHD;STA

Start condition hold time

260

–

160

–

tLOW

Clock LOW period

500

–

160

–

tHIGH

Clock HIGH period

260

–

tSU;DAT

tSU;DATA

Data in setup

–

tHD;DAT

tHD;DATA

Data in hold

–

tDH

Data output hold (from SCL at VIL)0

–

tR[10]

Input rise time

–

120

tF[10]

Input fall time

20 * (VDD / 5.5 V)

120

tSU;STO

STOP condition setup

260

–

160

–

tAA

tVD;DATA

SCL LOW to SDA Data Out Valid

–

450

–

130

tVD;ACK

ACK output valid time

–

450

–

130

tOF[10]

Output fall time from VIH min to VILmax

20 * (VDD / 5.5 V)

120

–

tBUF

Bus free before new transmission

500

–

300

–

tSP

Noise suppression time constant on SCL, SDA

–

Figure 18. Read Bus Timing Diagram

Figure 19. Write Bus Timing Diagram

tSU:SDA

Start

Stop Start

tBUF

tHIGH

1/fSCL

tLOW

tSP

Acknowledge

tHD:DAT

tSU:DAT

tAA

tDH

SCL

SDA

tSU:STO

Start

Stop Start

Acknowledge

tAA

tHD:DAT

tHD:STA

tSU:DAT

SCL

SDA

Notes

7. Test conditions assume signal transition time of 10 ns or less, timing reference levels of VDD/2, input pulse levels of 0 to VDD(typ), and output loading of the specified

IOL and 100 pF load capacitance shown in Figure 17.

8. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL(max).

9. Bus Load (Cb) considerations; Cb < 550 pF for I2C clock frequency (SCL) 1 MHz; Cb < 100 pF for SCL at 3.4 MHz.

10. These parameters are guaranteed by design and are not tested.

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